From 072287d0abdd640759fee1b1aa28a6ce69a23dfd Mon Sep 17 00:00:00 2001 From: nickci2002 Date: Wed, 2 Jul 2025 11:19:56 -0400 Subject: [PATCH] Updated V_CMP_U64 for future addons --- .../frontend/translate/translate.h | 1 - .../frontend/translate/vector_alu.cpp | 54 ++++--------------- 2 files changed, 11 insertions(+), 44 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h index 7257bea53..b5bfec344 100644 --- a/src/shader_recompiler/frontend/translate/translate.h +++ b/src/shader_recompiler/frontend/translate/translate.h @@ -231,7 +231,6 @@ public: void V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst); void V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst); void V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst); - void V_CMP_EQ_U64(ConditionOp op, const GcnInst& inst); void V_CMP_CLASS_F32(const GcnInst& inst); // VOP3a diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 857cc84e9..448622f0e 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -328,9 +328,9 @@ void Translator::EmitVectorAlu(const GcnInst& inst) { // V_CMP_{OP8}_U64 case Opcode::V_CMP_EQ_U64: - return V_CMP_EQ_U64(ConditionOp::EQ, inst); + return V_CMP_U64(ConditionOp::EQ, false, false, inst); case Opcode::V_CMP_NE_U64: - return V_CMP_EQ_U64(ConditionOp::LG, inst); + return V_CMP_U64(ConditionOp::LG, false, false, inst); case Opcode::V_CMP_CLASS_F32: return V_CMP_CLASS_F32(inst); @@ -998,46 +998,7 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const } } -// General case for V_CMP_U64 is not yet implemented -// void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) { -// const IR::U64 src0{GetSrc64(inst.src[0])}; -// const IR::U64 src1{GetSrc64(inst.src[1])}; -// const IR::U1 result = [&] { -// switch (op) { -// case ConditionOp::F: -// return ir.Imm1(false); -// case ConditionOp::TRU: -// return ir.Imm1(true); -// case ConditionOp::EQ: -// return ir.IEqual(src0, src1); -// case ConditionOp::LG: -// return ir.INotEqual(src0, src1); -// case ConditionOp::GT: -// return ir.IGreaterThan(src0, src1, is_signed); -// case ConditionOp::LT: -// return ir.ILessThan(src0, src1, is_signed); -// case ConditionOp::LE: -// return ir.ILessThanEqual(src0, src1, is_signed); -// case ConditionOp::GE: -// return ir.IGreaterThanEqual(src0, src1, is_signed); -// default: -// UNREACHABLE(); -// } -// }(); -// if (set_exec) { -// ir.SetExec(result); -// } -// switch (inst.dst[1].field) { -// case OperandField::VccLo: -// return ir.SetVcc(result); -// case OperandField::ScalarGPR: -// return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result); -// default: -// UNREACHABLE(); -// } -// } - -void Translator::V_CMP_EQ_U64(ConditionOp op, const GcnInst& inst) { +void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) { const IR::U64 src0{GetSrc64(inst.src[0])}; const IR::U64 src1{GetSrc64(inst.src[1])}; const IR::U1 result = [&] { @@ -1047,10 +1008,17 @@ void Translator::V_CMP_EQ_U64(ConditionOp op, const GcnInst& inst) { case ConditionOp::LG: // NE return ir.INotEqual(src0, src1); default: - UNREACHABLE_MSG("Unsupported V_CMP_EQ_U64 condition operation: {}", u32(op)); + UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op)); } }(); + if (is_signed) { + UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported"); + } + if (set_exec) { + UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported"); + } + switch (inst.dst[1].field) { case OperandField::VccLo: return ir.SetVcc(result);