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https://github.com/shadps4-emu/shadPS4.git
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ir: Perform degamma in shader when sampler sets force_degamma (#3420)
* ir: Perform degamma in shader when sampler sets force_degamma * specialization: Add srgb if image is sampled Might fix cases where sampler force_degamma is used with srgb image
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@@ -1169,6 +1169,10 @@ F32 IREmitter::FPLog2(const F32& value) {
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return Inst<F32>(Opcode::FPLog2, value);
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}
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F32 IREmitter::FPPow(const F32& x, const F32& y) {
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return Inst<F32>(Opcode::FPPow, x, y);
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}
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F32F64 IREmitter::FPRecip(const F32F64& value) {
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switch (value.Type()) {
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case Type::F32:
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@@ -228,6 +228,7 @@ public:
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[[nodiscard]] F32 FPSin(const F32& value);
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[[nodiscard]] F32 FPExp2(const F32& value);
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[[nodiscard]] F32 FPLog2(const F32& value);
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[[nodiscard]] F32 FPPow(const F32& x, const F32& y);
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[[nodiscard]] F32 FPLdexp(const F32& value, const U32& exp);
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[[nodiscard]] F32F64 FPRecip(const F32F64& value);
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[[nodiscard]] F32F64 FPRecipSqrt(const F32F64& value);
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@@ -283,6 +283,7 @@ OPCODE(FPRecipSqrt64, F64, F64,
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OPCODE(FPSqrt, F32, F32, )
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OPCODE(FPSin, F32, F32, )
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OPCODE(FPExp2, F32, F32, )
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OPCODE(FPPow, F32, F32, F32, )
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OPCODE(FPLdexp, F32, F32, U32, )
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OPCODE(FPCos, F32, F32, )
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OPCODE(FPLog2, F32, F32, )
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@@ -542,7 +542,7 @@ void PatchImageSharp(IR::Block& block, IR::Inst& inst, Info& info, Descriptors&
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ASSERT(image.GetType() != AmdGpu::ImageType::Invalid);
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// Patch image instruction if image is FMask.
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if (image.IsFmask()) {
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if (AmdGpu::IsFmask(image.GetDataFmt())) {
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ASSERT_MSG(!is_written, "FMask storage instructions are not supported");
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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@@ -830,8 +830,8 @@ IR::Value FixCubeCoords(IR::IREmitter& ir, const AmdGpu::Image& image, const IR:
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void PatchImageSampleArgs(IR::Block& block, IR::Inst& inst, Info& info,
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const ImageResource& image_res, const AmdGpu::Image& image) {
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const auto handle = inst.Arg(0);
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const auto sampler_res = info.samplers[(handle.U32() >> 16) & 0xFFFF];
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auto sampler = sampler_res.GetSharp(info);
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const auto& sampler_res = info.samplers[(handle.U32() >> 16) & 0xFFFF];
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const auto sampler = sampler_res.GetSharp(info);
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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@@ -1001,7 +1001,10 @@ void PatchImageSampleArgs(IR::Block& block, IR::Inst& inst, Info& info,
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return ir.ImageSampleImplicitLod(handle, coords, bias, offset, inst_info);
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}();
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const auto converted = ApplyReadNumberConversionVec4(ir, texel, image.GetNumberConversion());
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auto converted = ApplyReadNumberConversionVec4(ir, texel, image.GetNumberConversion());
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if (sampler.force_degamma && image.GetNumberFmt() != AmdGpu::NumberFormat::Srgb) {
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converted = ApplyForceDegamma(ir, texel, image.DstSelect());
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}
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inst.ReplaceUsesWith(converted);
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}
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@@ -4,7 +4,7 @@
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#pragma once
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "video_core/amdgpu/types.h"
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#include "video_core/amdgpu/pixel_format.h"
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namespace Shader::IR {
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@@ -21,6 +21,36 @@ inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::Comp
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return swizzled;
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}
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/// Converts gamma corrected value to linear space
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inline F32 ApplyGammaToLinear(IREmitter& ir, F32& c) {
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const F32 a =
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ir.FPPow(ir.FPMul(ir.FPAdd(c, ir.Imm32(0.055f)), ir.Imm32(1.0f / 1.055f)), ir.Imm32(2.4f));
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const F32 b = ir.FPMul(c, ir.Imm32(1.0f / 12.92f));
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return IR::F32{ir.Select(ir.FPGreaterThan(c, ir.Imm32(0.04045f)), a, b)};
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}
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inline Value ApplyForceDegamma(IREmitter& ir, const Value& value,
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const AmdGpu::CompMapping& mapping) {
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auto x = F32{ir.CompositeExtract(value, 0)};
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auto y = F32{ir.CompositeExtract(value, 1)};
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auto z = F32{ir.CompositeExtract(value, 2)};
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auto w = F32{ir.CompositeExtract(value, 3)};
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// Gamma correction is only applied to RGB components
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if (AmdGpu::IsRgb(mapping.r)) {
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x = ApplyGammaToLinear(ir, x);
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}
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if (AmdGpu::IsRgb(mapping.g)) {
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y = ApplyGammaToLinear(ir, y);
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}
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if (AmdGpu::IsRgb(mapping.b)) {
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z = ApplyGammaToLinear(ir, z);
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}
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if (AmdGpu::IsRgb(mapping.a)) {
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w = ApplyGammaToLinear(ir, w);
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}
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return ir.CompositeConstruct(x, y, z, w);
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}
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/// Applies a number conversion in the read direction.
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inline F32 ApplyReadNumberConversion(IREmitter& ir, const F32& value,
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const AmdGpu::NumberConversion& conversion) {
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