mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
update comments for current implementation
This commit is contained in:
Frodo Baggins
parent
b0dafd0501
commit
0b75adb7c8
@ -8,20 +8,21 @@
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namespace Shader {
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struct TessellationDataConstantBuffer {
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u32 m_lsStride;
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u32 m_hsCpStride; // HullStateConstants::m_cpStride != 0 ? HullStateConstants::m_cpStride :
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u32 ls_stride;
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u32 hs_cp_stride; // HullStateConstants::m_cpStride != 0 ? HullStateConstants::m_cpStride :
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// ls_stride
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u32 m_hsNumPatch; // num patches submitted in threadgroup
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u32 m_hsOutputBase; // HullStateConstants::m_numInputCP::m_cpStride != 0 ?
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u32 num_patches; // num patches submitted in threadgroup
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u32 hs_output_base; // HullStateConstants::m_numInputCP::m_cpStride != 0 ?
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// HullStateConstants::m_numInputCP * ls_stride * num_patches : 0
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u32 m_patchConstSize; // 16 * num_patch_attrs
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u32 m_patchConstBase; // hs_output_base + patch_output_size
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u32 m_patchOutputSize; // output_cp_stride * num_output_cp
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f32 m_offChipTessellationFactorThreshold;
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u32 m_firstEdgeTessFactorIndex;
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// basically 0 when passthrough
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u32 patch_const_size; // 16 * num_patch_attrs
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u32 patch_const_base; // hs_output_base + patch_output_size
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u32 patch_output_size; // output_cp_stride * num_output_cp_per_patch
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f32 off_chip_tessellation_factor_threshold;
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u32 first_edge_tess_factor_index;
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};
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// TODO comment
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// Assign names to dword fields of TessellationDataConstantBuffer
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enum class TessConstantAttribute : u32 {
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LsStride,
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HsCpStride,
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@ -129,7 +129,7 @@ void Translator::EmitPrologue() {
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// [8:12]: output control point id
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ir.SetVectorReg(IR::VectorReg::V1,
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ir.GetAttributeU32(IR::Attribute::PackedHullInvocationInfo));
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// TODO need PrimitiveId also like TES?
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// TODO need PrimitiveId also like TES? Havent seen it yet but probably V2
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break;
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}
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case LogicalStage::TessellationEval:
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@ -140,12 +140,8 @@ void Translator::EmitPrologue() {
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// V2 is similar to PrimitiveID but not the same. It seems to only be used in
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// compiler-generated address calculations. Its probably the patch id within the
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// patches running locally on a given VGT (or CU, whichever is the granularity of LDS
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// memory). So it is probably equal to PrimitiveID % #patches_per_VGT (or per CU).
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// We should be able to safely set V2 to 0, along with other special values read from the
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// tess constants buffer, since in the recompiled Vulkan shaders a thread can only
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// read/write control points and patch const attributes within the local patch. This (V2)
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// and other special values of TessellationDataConstantBuffer are (probably) just an
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// implementation detail from the ps4 shader compiler and only used for addressing.
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// memory)
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// Set to 0. See explanation in comment describing hull/domain passes
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ir.SetVectorReg(IR::VectorReg::V2, ir.Imm32(0u));
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// V3 is the actual PrimitiveID as intended by the shader author.
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ir.SetVectorReg(IR::VectorReg::V3, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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@ -1,6 +1,5 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <numeric>
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#include "common/assert.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/attribute.h"
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@ -9,31 +8,17 @@
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#include "shader_recompiler/ir/opcodes.h"
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#include "shader_recompiler/ir/pattern_matching.h"
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#include "shader_recompiler/ir/program.h"
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// TODO delelte
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#include "common/io_file.h"
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#include "common/path_util.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Optimization {
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static void DumpIR(IR::Program& program, std::string phase) {
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std::string s = IR::DumpProgram(program);
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using namespace Common::FS;
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const auto dump_dir = GetUserPath(PathType::ShaderDir) / "dumps";
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if (!std::filesystem::exists(dump_dir)) {
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std::filesystem::create_directories(dump_dir);
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}
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const auto filename =
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fmt::format("{}_{:#018x}.{}.ir.txt", program.info.stage, program.info.pgm_hash, phase);
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const auto file = IOFile{dump_dir / filename, FileAccessMode::Write};
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file.WriteString(s);
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};
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/**
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* Tessellation shaders pass outputs to the next shader using LDS.
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* The Hull shader stage receives input control points stored in LDS.
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*
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* These passes attempt to resolve LDS accesses to attribute accesses and correctly
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* write to the tessellation factor tables.
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*
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* The LDS layout is:
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* - TCS inputs for patch 0
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* - TCS inputs for patch 1
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@ -43,66 +28,111 @@ static void DumpIR(IR::Program& program, std::string phase) {
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* - TCS outputs for patch 1
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* - TCS outputs for patch 2
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* - ...
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* - Per-patch TCS outputs for patch 0
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* - Per-patch TCS outputs for patch 1
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* - Per-patch TCS outputs for patch 2
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* - PatchConst TCS outputs for patch 0
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* - PatchConst TCS outputs for patch 1
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* - PatchConst TCS outputs for patch 2
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*
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*
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* If the Hull stage does not write any new control points the driver will
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* optimize LDS layout so input and output control point spaces overlap.
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* (Passthrough)
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*
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* Tessellation factors are stored in the per-patch TCS output block
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* as well as a factor V# that is automatically bound by the driver.
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* The gnm driver requires a V# holding special constants to be bound
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* for reads by the shader.
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* The Hull and Domain shaders read values from this buffer which
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* contain size and offset information required to address input, output,
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* or PatchConst attributes within the current patch.
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* See the TessellationDataConstantBuffer struct to see the layout of this V#.
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*
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* This pass attempts to resolve LDS accesses to attribute accesses and correctly
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* write to the tessellation factor tables. For the latter we replace the
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* buffer store instruction to factor writes according to their offset.
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* Tessellation factors are stored to a special tessellation factor V# that is automatically bound
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* by the driver. This is the input to the fixed function tessellator that actually subdivides the
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* domain. We translate these to writes to SPIR-V builtins for tessellation factors in the Hull
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* shader.
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* The offset into the tess factor buffer determines which factor the shader is writing.
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* Additionally, most hull shaders seem to redundantly write tess factors to PatchConst
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* attributes, even if dead in the domain shader. We just treat these as generic PatchConst writes.
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*
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* LDS stores can either be output control point writes or per-patch data writes.
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* This is detected by looking at how the address is formed. In any case the calculation
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* will be of the form a * b + c. For output control points a = output_control_point_id
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* while for per-patch writes a = patch_id.
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* LDS reads in the Hull shader can be from input control points, and in the the Domain shader can
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* be hs output control points (output from the perspective of the Hull shader) and patchconst
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* values.
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* LDS stores in the Hull shader can either be output control point writes or per-patch
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* (PatchConst) data writes. The Domain shader exports attributes using EXP instructions, unless its
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* followed by the geometry stage (but we havent seen this yet), so nothing special there.
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* The address calculations can vary significantly and can't be easily pattern matched. We are at
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* the mercy of instruction selection the ps4 compiler wanted to use.
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* Generally though, they could look something like this:
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* Input control point:
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* addr = PatchIdInVgt * input_cp_stride * #input_cp_per_patch + index * input_cp_stride
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* + attr# * 16 + component
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* Output control point:
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* addr = #patches * input_cp_stride * #input_cp_per_patch
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* + PatchIdInVgt * output_patch_stride + InvocationID * output_cp_stride
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+ attr# * 16 + component
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* Per patch output:
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* addr = #patches * input_cp_stride * #cp_per_input_patch
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* + #patches * output_patch_stride
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* + PatchIdInVgt * per_patch_output_stride + attr# * 16 + component
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*
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* Both patch_id and output_control_point_id are packed in VGPR1 by the driver and shader
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* uses V_BFE_U32 to extract them. We use the starting bit_pos to determine which is which.
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* output_patch_stride and output_cp_stride are usually compile time constants in the gcn
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*
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* LDS reads are more tricky as amount of different calculations performed can vary.
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* The final result, if output control point space is distinct, is of the form:
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* patch_id * input_control_point_stride * num_control_points_per_input_patch + a
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* The value "a" can be anything in the range of [0, input_control_point_stride]
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* Hull shaders can probably also read output control points corresponding to other threads, like
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* shared memory (but we havent seen this yet).
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* ^ This is an UNREACHABLE for now. We may need to insert additional barriers if this happens.
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* They should also be able to read PatchConst values,
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* although not sure if this happens in practice.
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*
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* This pass does not attempt to deduce the exact attribute referenced by "a" but rather
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* only using "a" itself index into input attributes. Those are defined as an array in the shader
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* layout (location = 0) in vec4[num_control_points_per_input_patch] attr[];
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* ...
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* float value = attr[a / in_stride][(a % in_stride) >> 4][(a & 0xF) >> 2];
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* To determine which type of attribute (input, output, patchconst) we the check the users of
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* TessConstants V# reads to deduce which type of attribute a given load/store to LDS
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* is touching.
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*
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* This requires knowing in_stride which is not provided to us by the guest.
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* To deduce it we perform a breadth first search on the arguments of a DS_READ*
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* looking for a buffer load with offset = 0. This will be the buffer holding tessellation
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* constants and it contains the value of in_stride we can read at compile time.
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* In the Hull shader, both the PatchId within the VGT group (PatchIdInVgt) and the output control
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* point id (InvocationId) are packed in VGPR1 by the driver like
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* V1 = InvocationId << 8 | PatchIdInVgt
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* The shader typically uses V_BFE_(U|S)32 to extract them. We use the starting bit_pos to determine
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* which is which.
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*
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* NOTE: This pass must be run before constant propagation as it relies on relatively specific
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* pattern matching that might be mutated that that optimization pass.
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* This pass does not attempt to deduce the exact attribute referenced in a LDS load/store.
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* Instead, it feeds the address in the LDS load/store to the get/set Insts we use for TCS in/out's,
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* TES in's, and PatchConst in/out's.
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*
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* TCS/TES Input attributes:
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* We define input attributes using an array in the shader roughly like this:
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* // equivalent GLSL in TCS
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* layout (location = 0) in vec4 in_attrs[][NUM_INPUT_ATTRIBUTES];
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*
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* Here the NUM_INPUT_ATTRIBUTES is derived from the ls_stride member of the TessConstants V#.
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* We divide ls_stride (in bytes) by 16 to get the number of vec4 attributes.
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* For TES, the number of attributes comes from hs_cp_stride / 16.
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* The first (outer) dimension is unsized but corresponds to the number of vertices in the hs input
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* patch (for Hull) or the hs output patch (for Domain).
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*
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* For input reads in TCS or TES, we emit SPIR-V like:
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* float value = in_attrs[addr / ls_stride][(addr % ls_stride) >> 4][(addr & 0xF) >> 2];
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*
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* For output writes, we assume the control point index is InvocationId, since high level languages
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* impose that restriction (although maybe it's technically possible on hardware). So SPIR-V looks
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* like this:
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* layout (location = 0) in vec4 in_attrs[][NUM_OUTPUT_ATTRIBUTES];
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* out_attrs[InvocationId][(addr % hs_cp_stride) >> 4][(addr & 0xF) >> 2] = value;
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*
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* NUM_OUTPUT_ATTRIBUTES is derived by hs_cp_stride / 16, so it can link with the TES in_attrs
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* variable.
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*
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* Another challenge is the fact that the GCN shader needs to address attributes from LDS as a whole
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* which contains the attributes from many patches. On the other hand, higher level shading
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* languages restrict attribute access to the patch of the current thread, which is naturally a
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* restriction in SPIR-V also.
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* The addresses the ps4 compiler generates for loads/stores and the fact that LDS holds many
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* patches' attributes are just implementation details of the ps4 driver/compiler. To deal with
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* this, we can replace certain TessConstant V# reads with 0, which only contribute to the base
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* address of the current patch's attributes in LDS and not the indexes within the local patch.
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*
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* (A perfect implementation might need emulation of the VGTs in mesh/compute, loading/storing
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* attributes to buffers and not caring about whether they are hs input, hs output, or patchconst
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* attributes)
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*
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* TODO: need to be careful about reading from output arrays at idx other than InvocationID
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* Need SPIRV OpControlBarrier
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* "Wait for all active invocations within the specified Scope to reach the current point of
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* execution."
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* Must be placed in uniform control flow
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*/
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// Addr calculations look something like this, but can vary wildly due to decisions made by
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// the ps4 compiler (instruction selection, etc)
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// Input control point:
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// PrimitiveId * input_cp_stride * #cp_per_input_patch + index * input_cp_stride + (attr# * 16 +
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// component)
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// Output control point
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// #patches * input_cp_stride * #cp_per_input_patch + PrimitiveId * output_patch_stride +
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// InvocationID * output_cp_stride + (attr# * 16 + component)
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// Per patch output:
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// #patches * input_cp_stride * #cp_per_input_patch + #patches * output_patch_stride +
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// + PrimitiveId * per_patch_output_stride + (attr# * 16 + component)
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namespace {
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using namespace Shader::Optimiation::PatternMatching;
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@ -162,15 +192,9 @@ std::optional<TessSharpLocation> FindTessConstantSharp(IR::Inst* read_const_buff
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// is used as an addend to skip the region for input control points, and similarly
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// NumPatch * hs_cp_stride * #output_cp_in_patch is used to skip the region
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// for output control points.
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// The Input CP, Output CP, and PatchConst regions are laid out in that order for the
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// entire thread group, so seeing the TcsNumPatches attribute used in an addr calc should
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// increment the "region counter" by 1 for the given Load/WriteShared
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//
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// TODO this will break if AMD compiler used distributive property like
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// TODO: this will break if AMD compiler used distributive property like
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// TcsNumPatches * (ls_stride * #input_cp_in_patch + hs_cp_stride * #output_cp_in_patch)
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//
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// TODO can we just look at address post-constant folding, pull out all the constants
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// and find the interval it's inside of? (phis are still a problem here)
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class TessConstantUseWalker {
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public:
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void MarkTessAttributeUsers(IR::Inst* read_const_buffer, TessConstantAttribute attr) {
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@ -306,7 +330,6 @@ static bool TryOptimizeAddendInModulo(IR::Value addend, u32 stride, std::vector<
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// If any addend is divisible by stride, then we can replace it with 0 in the attribute
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// or component index calculation
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static IR::U32 TryOptimizeAddressModulo(IR::U32 addr, u32 stride, IR::IREmitter& ir) {
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#if 1
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std::vector<IR::U32> addends;
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if (TryOptimizeAddendInModulo(addr, stride, addends)) {
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addr = ir.Imm32(0);
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@ -314,10 +337,11 @@ static IR::U32 TryOptimizeAddressModulo(IR::U32 addr, u32 stride, IR::IREmitter&
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addr = ir.IAdd(addr, addend);
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}
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}
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#endif
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return addr;
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}
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// TODO: can optimize div in control point index similarly to mod
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// Read a TCS input (InputCP region) or TES input (OutputCP region)
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static IR::F32 ReadTessInputComponent(IR::U32 addr, const u32 stride, IR::IREmitter& ir,
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u32 off_dw) {
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@ -340,8 +364,6 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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IR::IREmitter ir{*block,
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IR::Block::InstructionList::s_iterator_to(inst)}; // TODO sink this
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const auto opcode = inst.GetOpcode();
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switch (opcode) {
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case IR::Opcode::StoreBufferU32:
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@ -352,6 +374,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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if (!info.globally_coherent) {
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break;
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}
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto GetValue = [&](IR::Value data) -> IR::F32 {
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if (auto* inst = data.TryInstRecursive();
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inst && inst->GetOpcode() == IR::Opcode::BitCastU32F32) {
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@ -389,7 +412,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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}
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return IR::PatchFactor(gcn_factor_idx);
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default:
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// TODO point domain types haven't been seen so far
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// Point domain types haven't been seen so far
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UNREACHABLE_MSG("Unhandled tess type");
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}
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};
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@ -412,6 +435,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::WriteSharedU32:
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case IR::Opcode::WriteSharedU64:
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case IR::Opcode::WriteSharedU128: {
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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const u32 num_dwords = opcode == IR::Opcode::WriteSharedU32
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? 1
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: (opcode == IR::Opcode::WriteSharedU64 ? 2 : 4);
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@ -457,6 +481,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::LoadSharedU32: {
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case IR::Opcode::LoadSharedU64:
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case IR::Opcode::LoadSharedU128:
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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const IR::U32 addr{inst.Arg(0)};
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AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
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const u32 num_dwords = opcode == IR::Opcode::LoadSharedU32
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@ -515,16 +540,15 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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ir.SetTcsGenericAttribute(attr_read, ir.Imm32(attr_no), ir.Imm32(comp));
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}
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}
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// TODO: wrap rest of program with if statement when passthrough?
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// copy passthrough attributes ...
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// We could wrap the rest of the program in an if stmt
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// CopyInputAttrsToOutputs(); // psuedocode
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// if (InvocationId == 0) {
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// program ...
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// PatchConstFunction();
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// }
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// But as long as we treat invocation ID as 0 for all threads, shouldn't matter functionally
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}
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}
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// TODO refactor
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void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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Info& info = program.info;
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@ -628,8 +652,7 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
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auto sharp_location = FindTessConstantSharp(&inst);
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if (sharp_location && sharp_location->ptr_base == info.tess_consts_ptr_base &&
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sharp_location->dword_off == info.tess_consts_dword_offset) {
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// Replace the load with a special attribute load (for readability and
|
||||
// easier pattern matching)
|
||||
// The shader is reading from the TessConstants V#
|
||||
IR::Value index = inst.Arg(1);
|
||||
|
||||
ASSERT_MSG(index.IsImmediate(),
|
||||
@ -643,10 +666,10 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
||||
case TessConstantAttribute::LsStride:
|
||||
// If not, we may need to make this runtime state for TES
|
||||
ASSERT(info.l_stage == LogicalStage::TessellationControl);
|
||||
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.m_lsStride));
|
||||
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.ls_stride));
|
||||
break;
|
||||
case TessConstantAttribute::HsCpStride:
|
||||
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.m_hsCpStride));
|
||||
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.hs_cp_stride));
|
||||
break;
|
||||
case TessConstantAttribute::HsNumPatch:
|
||||
case TessConstantAttribute::HsOutputBase:
|
||||
@ -659,12 +682,14 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
||||
// See the explanation for why we set V2 to 0 when emitting the prologue.
|
||||
inst.ReplaceUsesWithAndRemove(IR::Value(0u));
|
||||
break;
|
||||
// PatchConstSize:
|
||||
// PatchOutputSize:
|
||||
// OffChipTessellationFactorThreshold:
|
||||
// FirstEdgeTessFactorIndex:
|
||||
default:
|
||||
case Shader::TessConstantAttribute::PatchConstSize:
|
||||
case Shader::TessConstantAttribute::PatchOutputSize:
|
||||
case Shader::TessConstantAttribute::OffChipTessellationFactorThreshold:
|
||||
case Shader::TessConstantAttribute::FirstEdgeTessFactorIndex:
|
||||
// May need to replace PatchConstSize and PatchOutputSize with 0
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE_MSG("Read past end of TessConstantsBuffer");
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -675,8 +700,7 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
||||
// PatchConst attributes and tess factors. PatchConst should be easy, turn those into a single
|
||||
// vec4 array like in/out attrs. Not sure about tess factors.
|
||||
if (info.l_stage == LogicalStage::TessellationControl) {
|
||||
// Replace the BFEs on V1 (packed with patch id and output cp id) for easier pattern
|
||||
// matching
|
||||
// Replace the BFEs on V1 (packed with patch id within VGT and output cp id)
|
||||
for (IR::Block* block : program.blocks) {
|
||||
for (auto it = block->Instructions().begin(); it != block->Instructions().end(); it++) {
|
||||
IR::Inst& inst = *it;
|
||||
@ -686,6 +710,8 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
||||
MatchU32(0), MatchU32(8))
|
||||
.Match(IR::Value{&inst})) {
|
||||
IR::IREmitter emit(*block, it);
|
||||
// This is the patch id within the VGT, not the actual PrimitiveId
|
||||
// in the draw
|
||||
IR::Value replacement(0u);
|
||||
inst.ReplaceUsesWithAndRemove(replacement);
|
||||
} else if (M_BITFIELDUEXTRACT(
|
||||
@ -698,7 +724,7 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
||||
IR::Value replacement;
|
||||
if (runtime_info.hs_info.IsPassthrough()) {
|
||||
// Deal with annoying pattern in BB where InvocationID use makes no
|
||||
// sense (in addr calculation for patchconst write)
|
||||
// sense (in addr calculation for patchconst or tess factor write)
|
||||
replacement = ir.Imm32(0);
|
||||
} else {
|
||||
replacement = ir.GetAttributeU32(IR::Attribute::InvocationId);
|
||||
|
||||
@ -98,7 +98,7 @@ struct VertexRuntimeInfo {
|
||||
}
|
||||
|
||||
void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) {
|
||||
hs_output_cp_stride = tess_constants.m_hsCpStride;
|
||||
hs_output_cp_stride = tess_constants.hs_cp_stride;
|
||||
}
|
||||
};
|
||||
|
||||
@ -135,9 +135,9 @@ struct HullRuntimeInfo {
|
||||
}
|
||||
|
||||
void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) {
|
||||
ls_stride = tess_constants.m_lsStride;
|
||||
hs_output_cp_stride = tess_constants.m_hsCpStride;
|
||||
hs_output_base = tess_constants.m_hsOutputBase;
|
||||
ls_stride = tess_constants.ls_stride;
|
||||
hs_output_cp_stride = tess_constants.hs_cp_stride;
|
||||
hs_output_base = tess_constants.hs_output_base;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
@ -101,7 +101,7 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Stage stage, LogicalStage l_
|
||||
const auto params = Liverpool::GetParams(*pgm);
|
||||
const auto& hull_info = program_cache.at(params.hash)->info;
|
||||
hull_info.ReadTessConstantBuffer(tess_constants);
|
||||
info.ls_info.ls_stride = tess_constants.m_lsStride;
|
||||
info.ls_info.ls_stride = tess_constants.ls_stride;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user