diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp index 4f9e6040e..03016726c 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp @@ -66,56 +66,6 @@ Id EmitCompositeShuffleU32x4(EmitContext& ctx, Id composite1, Id composite2, u32 return ctx.OpVectorShuffle(ctx.U32[4], composite1, composite2, comp0, comp1, comp2, comp3); } -Id EmitCompositeConstructF16x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) { - return EmitCompositeConstruct(ctx, inst, ctx.F16[2], e1, e2); -} - -Id EmitCompositeConstructF16x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) { - return EmitCompositeConstruct(ctx, inst, ctx.F16[3], e1, e2, e3); -} - -Id EmitCompositeConstructF16x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) { - return EmitCompositeConstruct(ctx, inst, ctx.F16[4], e1, e2, e3, e4); -} - -Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index) { - return ctx.OpCompositeExtract(ctx.F16[1], composite, index); -} - -Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index) { - return ctx.OpCompositeExtract(ctx.F16[1], composite, index); -} - -Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index) { - return ctx.OpCompositeExtract(ctx.F16[1], composite, index); -} - -Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F16[2], object, composite, index); -} - -Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F16[3], object, composite, index); -} - -Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F16[4], object, composite, index); -} - -Id EmitCompositeShuffleF16x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) { - return ctx.OpVectorShuffle(ctx.F16[2], composite1, composite2, comp0, comp1); -} - -Id EmitCompositeShuffleF16x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2) { - return ctx.OpVectorShuffle(ctx.F16[3], composite1, composite2, comp0, comp1, comp2); -} - -Id EmitCompositeShuffleF16x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2, u32 comp3) { - return ctx.OpVectorShuffle(ctx.F16[4], composite1, composite2, comp0, comp1, comp2, comp3); -} - Id EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) { return EmitCompositeConstruct(ctx, inst, ctx.F32[2], e1, e2); } @@ -170,54 +120,4 @@ Id EmitCompositeShuffleF32x4(EmitContext& ctx, Id composite1, Id composite2, u32 return ctx.OpVectorShuffle(ctx.F32[4], composite1, composite2, comp0, comp1, comp2, comp3); } -void EmitCompositeConstructF64x2(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -void EmitCompositeConstructF64x3(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -void EmitCompositeConstructF64x4(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -void EmitCompositeExtractF64x2(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -void EmitCompositeExtractF64x3(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -void EmitCompositeExtractF64x4(EmitContext&) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F64[2], object, composite, index); -} - -Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F64[3], object, composite, index); -} - -Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index) { - return ctx.OpCompositeInsert(ctx.F64[4], object, composite, index); -} - -Id EmitCompositeShuffleF64x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) { - return ctx.OpVectorShuffle(ctx.F64[2], composite1, composite2, comp0, comp1); -} - -Id EmitCompositeShuffleF64x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2) { - return ctx.OpVectorShuffle(ctx.F64[3], composite1, composite2, comp0, comp1, comp2); -} - -Id EmitCompositeShuffleF64x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2, u32 comp3) { - return ctx.OpVectorShuffle(ctx.F64[4], composite1, composite2, comp0, comp1, comp2, comp3); -} - } // namespace Shader::Backend::SPIRV diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp index 2f4984f57..8da66e8a4 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp @@ -23,10 +23,6 @@ Id ExtractS8(EmitContext& ctx, Id value) { } } // Anonymous namespace -Id EmitConvertS16F16(EmitContext& ctx, Id value) { - return ctx.OpSConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); -} - Id EmitConvertS16F32(EmitContext& ctx, Id value) { return ctx.OpSConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); } @@ -35,10 +31,6 @@ Id EmitConvertS16F64(EmitContext& ctx, Id value) { return ctx.OpSConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); } -Id EmitConvertS32F16(EmitContext& ctx, Id value) { - return ctx.OpConvertFToS(ctx.U32[1], value); -} - Id EmitConvertS32F32(EmitContext& ctx, Id value) { return ctx.OpConvertFToS(ctx.U32[1], value); } @@ -47,10 +39,6 @@ Id EmitConvertS32F64(EmitContext& ctx, Id value) { return ctx.OpConvertFToS(ctx.U32[1], value); } -Id EmitConvertS64F16(EmitContext& ctx, Id value) { - return ctx.OpConvertFToS(ctx.U64, value); -} - Id EmitConvertS64F32(EmitContext& ctx, Id value) { return ctx.OpConvertFToS(ctx.U64, value); } @@ -59,10 +47,6 @@ Id EmitConvertS64F64(EmitContext& ctx, Id value) { return ctx.OpConvertFToS(ctx.U64, value); } -Id EmitConvertU16F16(EmitContext& ctx, Id value) { - return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); -} - Id EmitConvertU16F32(EmitContext& ctx, Id value) { return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); } @@ -71,10 +55,6 @@ Id EmitConvertU16F64(EmitContext& ctx, Id value) { return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); } -Id EmitConvertU32F16(EmitContext& ctx, Id value) { - return ctx.OpConvertFToU(ctx.U32[1], value); -} - Id EmitConvertU32F32(EmitContext& ctx, Id value) { return ctx.OpConvertFToU(ctx.U32[1], value); } @@ -83,10 +63,6 @@ Id EmitConvertU32F64(EmitContext& ctx, Id value) { return ctx.OpConvertFToU(ctx.U32[1], value); } -Id EmitConvertU64F16(EmitContext& ctx, Id value) { - return ctx.OpConvertFToU(ctx.U64, value); -} - Id EmitConvertU64F32(EmitContext& ctx, Id value) { return ctx.OpConvertFToU(ctx.U64, value); } @@ -119,38 +95,6 @@ Id EmitConvertF64F32(EmitContext& ctx, Id value) { return ctx.OpFConvert(ctx.F64[1], value); } -Id EmitConvertF16S8(EmitContext& ctx, Id value) { - return ctx.OpConvertSToF(ctx.F16[1], ExtractS8(ctx, value)); -} - -Id EmitConvertF16S16(EmitContext& ctx, Id value) { - return ctx.OpConvertSToF(ctx.F16[1], ExtractS16(ctx, value)); -} - -Id EmitConvertF16S32(EmitContext& ctx, Id value) { - return ctx.OpConvertSToF(ctx.F16[1], value); -} - -Id EmitConvertF16S64(EmitContext& ctx, Id value) { - return ctx.OpConvertSToF(ctx.F16[1], value); -} - -Id EmitConvertF16U8(EmitContext& ctx, Id value) { - return ctx.OpConvertUToF(ctx.F16[1], ExtractU8(ctx, value)); -} - -Id EmitConvertF16U16(EmitContext& ctx, Id value) { - return ctx.OpConvertUToF(ctx.F16[1], ExtractU16(ctx, value)); -} - -Id EmitConvertF16U32(EmitContext& ctx, Id value) { - return ctx.OpConvertUToF(ctx.F16[1], value); -} - -Id EmitConvertF16U64(EmitContext& ctx, Id value) { - return ctx.OpConvertUToF(ctx.F16[1], value); -} - Id EmitConvertF32S8(EmitContext& ctx, Id value) { return ctx.OpConvertSToF(ctx.F32[1], ExtractS8(ctx, value)); } diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp index 648740c82..66d400c7d 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp @@ -11,10 +11,6 @@ Id Decorate(EmitContext& ctx, IR::Inst* inst, Id op) { return op; } -Id EmitFPAbs16(EmitContext& ctx, Id value) { - return ctx.OpFAbs(ctx.F16[1], value); -} - Id EmitFPAbs32(EmitContext& ctx, Id value) { return ctx.OpFAbs(ctx.F32[1], value); } @@ -23,10 +19,6 @@ Id EmitFPAbs64(EmitContext& ctx, Id value) { return ctx.OpFAbs(ctx.F64[1], value); } -Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { - return Decorate(ctx, inst, ctx.OpFAdd(ctx.F16[1], a, b)); -} - Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { return Decorate(ctx, inst, ctx.OpFAdd(ctx.F32[1], a, b)); } @@ -39,10 +31,6 @@ Id EmitFPSub32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { return Decorate(ctx, inst, ctx.OpFSub(ctx.F32[1], a, b)); } -Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) { - return Decorate(ctx, inst, ctx.OpFma(ctx.F16[1], a, b, c)); -} - Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) { return Decorate(ctx, inst, ctx.OpFma(ctx.F32[1], a, b, c)); } @@ -97,10 +85,6 @@ Id EmitFPMedTri32(EmitContext& ctx, Id a, Id b, Id c) { return ctx.OpFMax(ctx.F32[1], ctx.OpFMin(ctx.F32[1], a, b), mmx); } -Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { - return Decorate(ctx, inst, ctx.OpFMul(ctx.F16[1], a, b)); -} - Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { return Decorate(ctx, inst, ctx.OpFMul(ctx.F32[1], a, b)); } @@ -117,10 +101,6 @@ Id EmitFPDiv64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { return Decorate(ctx, inst, ctx.OpFDiv(ctx.F64[1], a, b)); } -Id EmitFPNeg16(EmitContext& ctx, Id value) { - return ctx.OpFNegate(ctx.F16[1], value); -} - Id EmitFPNeg32(EmitContext& ctx, Id value) { return ctx.OpFNegate(ctx.F32[1], value); } @@ -173,12 +153,6 @@ Id EmitFPSqrt(EmitContext& ctx, Id value) { return ctx.OpSqrt(ctx.F32[1], value); } -Id EmitFPSaturate16(EmitContext& ctx, Id value) { - const Id zero{ctx.Constant(ctx.F16[1], u16{0})}; - const Id one{ctx.Constant(ctx.F16[1], u16{0x3c00})}; - return ctx.OpFClamp(ctx.F16[1], value, zero, one); -} - Id EmitFPSaturate32(EmitContext& ctx, Id value) { const Id zero{ctx.ConstF32(f32{0.0})}; const Id one{ctx.ConstF32(f32{1.0})}; @@ -191,10 +165,6 @@ Id EmitFPSaturate64(EmitContext& ctx, Id value) { return ctx.OpFClamp(ctx.F64[1], value, zero, one); } -Id EmitFPClamp16(EmitContext& ctx, Id value, Id min_value, Id max_value) { - return ctx.OpFClamp(ctx.F16[1], value, min_value, max_value); -} - Id EmitFPClamp32(EmitContext& ctx, Id value, Id min_value, Id max_value) { return ctx.OpFClamp(ctx.F32[1], value, min_value, max_value); } @@ -203,10 +173,6 @@ Id EmitFPClamp64(EmitContext& ctx, Id value, Id min_value, Id max_value) { return ctx.OpFClamp(ctx.F64[1], value, min_value, max_value); } -Id EmitFPRoundEven16(EmitContext& ctx, Id value) { - return ctx.OpRoundEven(ctx.F16[1], value); -} - Id EmitFPRoundEven32(EmitContext& ctx, Id value) { return ctx.OpRoundEven(ctx.F32[1], value); } @@ -215,10 +181,6 @@ Id EmitFPRoundEven64(EmitContext& ctx, Id value) { return ctx.OpRoundEven(ctx.F64[1], value); } -Id EmitFPFloor16(EmitContext& ctx, Id value) { - return ctx.OpFloor(ctx.F16[1], value); -} - Id EmitFPFloor32(EmitContext& ctx, Id value) { return ctx.OpFloor(ctx.F32[1], value); } @@ -227,10 +189,6 @@ Id EmitFPFloor64(EmitContext& ctx, Id value) { return ctx.OpFloor(ctx.F64[1], value); } -Id EmitFPCeil16(EmitContext& ctx, Id value) { - return ctx.OpCeil(ctx.F16[1], value); -} - Id EmitFPCeil32(EmitContext& ctx, Id value) { return ctx.OpCeil(ctx.F32[1], value); } @@ -239,10 +197,6 @@ Id EmitFPCeil64(EmitContext& ctx, Id value) { return ctx.OpCeil(ctx.F64[1], value); } -Id EmitFPTrunc16(EmitContext& ctx, Id value) { - return ctx.OpTrunc(ctx.F16[1], value); -} - Id EmitFPTrunc32(EmitContext& ctx, Id value) { return ctx.OpTrunc(ctx.F32[1], value); } diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_instructions.h b/src/shader_recompiler/backend/spirv/emit_spirv_instructions.h index 55e7536d2..80968eaf0 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_instructions.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv_instructions.h @@ -174,20 +174,6 @@ Id EmitCompositeShuffleU32x3(EmitContext& ctx, Id composite1, Id composite2, u32 u32 comp2); Id EmitCompositeShuffleU32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, u32 comp2, u32 comp3); -Id EmitCompositeConstructF16x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2); -Id EmitCompositeConstructF16x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3); -Id EmitCompositeConstructF16x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4); -Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index); -Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index); -Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index); -Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeShuffleF16x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1); -Id EmitCompositeShuffleF16x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2); -Id EmitCompositeShuffleF16x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2, u32 comp3); Id EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2); Id EmitCompositeConstructF32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3); Id EmitCompositeConstructF32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4); @@ -203,28 +189,9 @@ Id EmitCompositeShuffleF32x3(EmitContext& ctx, Id composite1, Id composite2, u32 u32 comp2); Id EmitCompositeShuffleF32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, u32 comp2, u32 comp3); -void EmitCompositeConstructF64x2(EmitContext& ctx); -void EmitCompositeConstructF64x3(EmitContext& ctx); -void EmitCompositeConstructF64x4(EmitContext& ctx); -void EmitCompositeExtractF64x2(EmitContext& ctx); -void EmitCompositeExtractF64x3(EmitContext& ctx); -void EmitCompositeExtractF64x4(EmitContext& ctx); -Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index); -Id EmitCompositeShuffleF64x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1); -Id EmitCompositeShuffleF64x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2); -Id EmitCompositeShuffleF64x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1, - u32 comp2, u32 comp3); Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value); -Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value); -Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value); -Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value); -Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value); -Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitBitCastU16F16(EmitContext& ctx, Id value); Id EmitBitCastU32F32(EmitContext& ctx, Id value); Id EmitBitCastF16U16(EmitContext& ctx, Id value); @@ -261,14 +228,11 @@ Id EmitPackUint2_10_10_10(EmitContext& ctx, Id value); Id EmitUnpackUint2_10_10_10(EmitContext& ctx, Id value); Id EmitPackSint2_10_10_10(EmitContext& ctx, Id value); Id EmitUnpackSint2_10_10_10(EmitContext& ctx, Id value); -Id EmitFPAbs16(EmitContext& ctx, Id value); Id EmitFPAbs32(EmitContext& ctx, Id value); Id EmitFPAbs64(EmitContext& ctx, Id value); -Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPSub32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); -Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); Id EmitFPMax32(EmitContext& ctx, Id a, Id b, bool is_legacy = false); @@ -278,12 +242,10 @@ Id EmitFPMin64(EmitContext& ctx, Id a, Id b); Id EmitFPMinTri32(EmitContext& ctx, Id a, Id b, Id c); Id EmitFPMaxTri32(EmitContext& ctx, Id a, Id b, Id c); Id EmitFPMedTri32(EmitContext& ctx, Id a, Id b, Id c); -Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPDiv32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); Id EmitFPDiv64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); -Id EmitFPNeg16(EmitContext& ctx, Id value); Id EmitFPNeg32(EmitContext& ctx, Id value); Id EmitFPNeg64(EmitContext& ctx, Id value); Id EmitFPSin(EmitContext& ctx, Id value); @@ -297,22 +259,16 @@ Id EmitFPRecip64(EmitContext& ctx, Id value); Id EmitFPRecipSqrt32(EmitContext& ctx, Id value); Id EmitFPRecipSqrt64(EmitContext& ctx, Id value); Id EmitFPSqrt(EmitContext& ctx, Id value); -Id EmitFPSaturate16(EmitContext& ctx, Id value); Id EmitFPSaturate32(EmitContext& ctx, Id value); Id EmitFPSaturate64(EmitContext& ctx, Id value); -Id EmitFPClamp16(EmitContext& ctx, Id value, Id min_value, Id max_value); Id EmitFPClamp32(EmitContext& ctx, Id value, Id min_value, Id max_value); Id EmitFPClamp64(EmitContext& ctx, Id value, Id min_value, Id max_value); -Id EmitFPRoundEven16(EmitContext& ctx, Id value); Id EmitFPRoundEven32(EmitContext& ctx, Id value); Id EmitFPRoundEven64(EmitContext& ctx, Id value); -Id EmitFPFloor16(EmitContext& ctx, Id value); Id EmitFPFloor32(EmitContext& ctx, Id value); Id EmitFPFloor64(EmitContext& ctx, Id value); -Id EmitFPCeil16(EmitContext& ctx, Id value); Id EmitFPCeil32(EmitContext& ctx, Id value); Id EmitFPCeil64(EmitContext& ctx, Id value); -Id EmitFPTrunc16(EmitContext& ctx, Id value); Id EmitFPTrunc32(EmitContext& ctx, Id value); Id EmitFPTrunc64(EmitContext& ctx, Id value); Id EmitFPFract32(EmitContext& ctx, Id value); @@ -321,43 +277,30 @@ Id EmitFPFrexpSig32(EmitContext& ctx, Id value); Id EmitFPFrexpSig64(EmitContext& ctx, Id value); Id EmitFPFrexpExp32(EmitContext& ctx, Id value); Id EmitFPFrexpExp64(EmitContext& ctx, Id value); -Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs); Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs); -Id EmitFPIsNan16(EmitContext& ctx, Id value); Id EmitFPIsNan32(EmitContext& ctx, Id value); Id EmitFPIsNan64(EmitContext& ctx, Id value); Id EmitFPIsInf32(EmitContext& ctx, Id value); @@ -437,22 +380,16 @@ Id EmitLogicalOr(EmitContext& ctx, Id a, Id b); Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b); Id EmitLogicalXor(EmitContext& ctx, Id a, Id b); Id EmitLogicalNot(EmitContext& ctx, Id value); -Id EmitConvertS16F16(EmitContext& ctx, Id value); Id EmitConvertS16F32(EmitContext& ctx, Id value); Id EmitConvertS16F64(EmitContext& ctx, Id value); -Id EmitConvertS32F16(EmitContext& ctx, Id value); Id EmitConvertS32F32(EmitContext& ctx, Id value); Id EmitConvertS32F64(EmitContext& ctx, Id value); -Id EmitConvertS64F16(EmitContext& ctx, Id value); Id EmitConvertS64F32(EmitContext& ctx, Id value); Id EmitConvertS64F64(EmitContext& ctx, Id value); -Id EmitConvertU16F16(EmitContext& ctx, Id value); Id EmitConvertU16F32(EmitContext& ctx, Id value); Id EmitConvertU16F64(EmitContext& ctx, Id value); -Id EmitConvertU32F16(EmitContext& ctx, Id value); Id EmitConvertU32F32(EmitContext& ctx, Id value); Id EmitConvertU32F64(EmitContext& ctx, Id value); -Id EmitConvertU64F16(EmitContext& ctx, Id value); Id EmitConvertU64F32(EmitContext& ctx, Id value); Id EmitConvertU64F64(EmitContext& ctx, Id value); Id EmitConvertU64U32(EmitContext& ctx, Id value); @@ -461,14 +398,6 @@ Id EmitConvertF16F32(EmitContext& ctx, Id value); Id EmitConvertF32F16(EmitContext& ctx, Id value); Id EmitConvertF32F64(EmitContext& ctx, Id value); Id EmitConvertF64F32(EmitContext& ctx, Id value); -Id EmitConvertF16S8(EmitContext& ctx, Id value); -Id EmitConvertF16S16(EmitContext& ctx, Id value); -Id EmitConvertF16S32(EmitContext& ctx, Id value); -Id EmitConvertF16S64(EmitContext& ctx, Id value); -Id EmitConvertF16U8(EmitContext& ctx, Id value); -Id EmitConvertF16U16(EmitContext& ctx, Id value); -Id EmitConvertF16U32(EmitContext& ctx, Id value); -Id EmitConvertF16U64(EmitContext& ctx, Id value); Id EmitConvertF32S8(EmitContext& ctx, Id value); Id EmitConvertF32S16(EmitContext& ctx, Id value); Id EmitConvertF32S32(EmitContext& ctx, Id value); diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp index 49857e28f..1bfe4ea3c 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp @@ -10,32 +10,12 @@ Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value) { return ctx.OpSelect(ctx.U1[1], cond, true_value, false_value); } -Id EmitSelectU8(EmitContext&, Id, Id, Id) { - UNREACHABLE_MSG("SPIR-V Instruction"); -} - -Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value) { - return ctx.OpSelect(ctx.U16, cond, true_value, false_value); -} - Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value) { return ctx.OpSelect(ctx.U32[1], cond, true_value, false_value); } -Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value) { - return ctx.OpSelect(ctx.U64, cond, true_value, false_value); -} - -Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value) { - return ctx.OpSelect(ctx.F16[1], cond, true_value, false_value); -} - Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value) { return ctx.OpSelect(ctx.F32[1], cond, true_value, false_value); } -Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value) { - return ctx.OpSelect(ctx.F64[1], cond, true_value, false_value); -} - } // namespace Shader::Backend::SPIRV diff --git a/src/shader_recompiler/backend/spirv/spirv_emit_context.cpp b/src/shader_recompiler/backend/spirv/spirv_emit_context.cpp index 4152420d0..a57cd47f6 100644 --- a/src/shader_recompiler/backend/spirv/spirv_emit_context.cpp +++ b/src/shader_recompiler/backend/spirv/spirv_emit_context.cpp @@ -122,7 +122,6 @@ void EmitContext::DefineArithmeticTypes() { S16 = Name(TypeSInt(16), "i16_id"); if (info.uses_fp16) { F16[1] = Name(TypeFloat(16), "f16_id"); - U16 = Name(TypeUInt(16), "u16_id"); } if (info.uses_fp64) { F64[1] = Name(TypeFloat(64), "f64_id"); diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index de43eb8da..095358766 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -740,14 +740,33 @@ void Translator::V_CVT_I32_F32(const GcnInst& inst) { void Translator::V_CVT_F16_F32(const GcnInst& inst) { const IR::F32 src0 = GetSrc(inst.src[0]); - const IR::F16 src0fp16 = ir.FPConvert(16, src0); - SetDst(inst.dst[0], ir.UConvert(32, ir.BitCast(src0fp16))); + + IR::U32 src0fp16; + if (profile.support_float16) { + const IR::F16 converted = ir.FPConvert(16, src0); + src0fp16 = ir.UConvert(32, ir.BitCast(converted)); + } else { + const IR::U32 packed = + ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(src0, ir.Imm32(0.f))); + src0fp16 = ir.BitFieldExtract(packed, ir.Imm32(0U), ir.Imm32(16U)); + } + + SetDst(inst.dst[0], src0fp16); } void Translator::V_CVT_F32_F16(const GcnInst& inst) { const IR::U32 src0 = GetSrc(inst.src[0]); - const IR::U16 src0l = ir.UConvert(16, src0); - SetDst(inst.dst[0], ir.FPConvert(32, ir.BitCast(src0l))); + + IR::F32 src0l; + if (profile.support_float16) { + const IR::U16 converted = ir.UConvert(16, src0); + src0l = ir.FPConvert(32, ir.BitCast(converted)); + } else { + const IR::Value unpacked = ir.Unpack2x16(AmdGpu::NumberFormat::Float, src0); + src0l = IR::F32{ir.CompositeExtract(unpacked, 0)}; + } + + SetDst(inst.dst[0], src0l); } void Translator::V_CVT_RPI_I32_F32(const GcnInst& inst) { diff --git a/src/shader_recompiler/ir/ir_emitter.cpp b/src/shader_recompiler/ir/ir_emitter.cpp index cbe7fc16f..8363cee0a 100644 --- a/src/shader_recompiler/ir/ir_emitter.cpp +++ b/src/shader_recompiler/ir/ir_emitter.cpp @@ -708,14 +708,10 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2) { return Inst(Opcode::CompositeConstructU32x2, e1, e2); case Type::U32x2: return Inst(Opcode::CompositeConstructU32x2x2, e1, e2); - case Type::F16: - return Inst(Opcode::CompositeConstructF16x2, e1, e2); case Type::F32: return Inst(Opcode::CompositeConstructF32x2, e1, e2); case Type::F32x2: return Inst(Opcode::CompositeConstructF32x2x2, e1, e2); - case Type::F64: - return Inst(Opcode::CompositeConstructF64x2, e1, e2); default: ThrowInvalidType(e1.Type()); } @@ -728,12 +724,8 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu switch (e1.Type()) { case Type::U32: return Inst(Opcode::CompositeConstructU32x3, e1, e2, e3); - case Type::F16: - return Inst(Opcode::CompositeConstructF16x3, e1, e2, e3); case Type::F32: return Inst(Opcode::CompositeConstructF32x3, e1, e2, e3); - case Type::F64: - return Inst(Opcode::CompositeConstructF64x3, e1, e2, e3); default: ThrowInvalidType(e1.Type()); } @@ -748,12 +740,8 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu switch (e1.Type()) { case Type::U32: return Inst(Opcode::CompositeConstructU32x4, e1, e2, e3, e4); - case Type::F16: - return Inst(Opcode::CompositeConstructF16x4, e1, e2, e3, e4); case Type::F32: return Inst(Opcode::CompositeConstructF32x4, e1, e2, e3, e4); - case Type::F64: - return Inst(Opcode::CompositeConstructF64x4, e1, e2, e3, e4); default: ThrowInvalidType(e1.Type()); } @@ -787,24 +775,12 @@ Value IREmitter::CompositeExtract(const Value& vector, size_t element) { return read(Opcode::CompositeExtractU32x3, 3); case Type::U32x4: return read(Opcode::CompositeExtractU32x4, 4); - case Type::F16x2: - return read(Opcode::CompositeExtractF16x2, 2); - case Type::F16x3: - return read(Opcode::CompositeExtractF16x3, 3); - case Type::F16x4: - return read(Opcode::CompositeExtractF16x4, 4); case Type::F32x2: return read(Opcode::CompositeExtractF32x2, 2); case Type::F32x3: return read(Opcode::CompositeExtractF32x3, 3); case Type::F32x4: return read(Opcode::CompositeExtractF32x4, 4); - case Type::F64x2: - return read(Opcode::CompositeExtractF64x2, 2); - case Type::F64x3: - return read(Opcode::CompositeExtractF64x3, 3); - case Type::F64x4: - return read(Opcode::CompositeExtractF64x4, 4); default: ThrowInvalidType(vector.Type()); } @@ -824,24 +800,12 @@ Value IREmitter::CompositeInsert(const Value& vector, const Value& object, size_ return insert(Opcode::CompositeInsertU32x3, 3); case Type::U32x4: return insert(Opcode::CompositeInsertU32x4, 4); - case Type::F16x2: - return insert(Opcode::CompositeInsertF16x2, 2); - case Type::F16x3: - return insert(Opcode::CompositeInsertF16x3, 3); - case Type::F16x4: - return insert(Opcode::CompositeInsertF16x4, 4); case Type::F32x2: return insert(Opcode::CompositeInsertF32x2, 2); case Type::F32x3: return insert(Opcode::CompositeInsertF32x3, 3); case Type::F32x4: return insert(Opcode::CompositeInsertF32x4, 4); - case Type::F64x2: - return insert(Opcode::CompositeInsertF64x2, 2); - case Type::F64x3: - return insert(Opcode::CompositeInsertF64x3, 3); - case Type::F64x4: - return insert(Opcode::CompositeInsertF64x4, 4); default: ThrowInvalidType(vector.Type()); } @@ -862,12 +826,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si switch (vector1.Type()) { case Type::U32x4: return shuffle(Opcode::CompositeShuffleU32x2); - case Type::F16x4: - return shuffle(Opcode::CompositeShuffleF16x2); case Type::F32x4: return shuffle(Opcode::CompositeShuffleF32x2); - case Type::F64x4: - return shuffle(Opcode::CompositeShuffleF64x2); default: ThrowInvalidType(vector1.Type()); } @@ -888,12 +848,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si switch (vector1.Type()) { case Type::U32x4: return shuffle(Opcode::CompositeShuffleU32x3); - case Type::F16x4: - return shuffle(Opcode::CompositeShuffleF16x3); case Type::F32x4: return shuffle(Opcode::CompositeShuffleF32x3); - case Type::F64x4: - return shuffle(Opcode::CompositeShuffleF64x3); default: ThrowInvalidType(vector1.Type()); } @@ -916,12 +872,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si switch (vector1.Type()) { case Type::U32x4: return shuffle(Opcode::CompositeShuffleU32x4); - case Type::F16x4: - return shuffle(Opcode::CompositeShuffleF16x4); case Type::F32x4: return shuffle(Opcode::CompositeShuffleF32x4); - case Type::F64x4: - return shuffle(Opcode::CompositeShuffleF64x4); default: ThrowInvalidType(vector1.Type()); } @@ -934,18 +886,10 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu switch (true_value.Type()) { case Type::U1: return Inst(Opcode::SelectU1, condition, true_value, false_value); - case Type::U8: - return Inst(Opcode::SelectU8, condition, true_value, false_value); - case Type::U16: - return Inst(Opcode::SelectU16, condition, true_value, false_value); case Type::U32: return Inst(Opcode::SelectU32, condition, true_value, false_value); - case Type::U64: - return Inst(Opcode::SelectU64, condition, true_value, false_value); case Type::F32: return Inst(Opcode::SelectF32, condition, true_value, false_value); - case Type::F64: - return Inst(Opcode::SelectF64, condition, true_value, false_value); default: UNREACHABLE_MSG("Invalid type {}", true_value.Type()); } diff --git a/src/shader_recompiler/ir/opcodes.inc b/src/shader_recompiler/ir/opcodes.inc index 3b907360c..4875375bc 100644 --- a/src/shader_recompiler/ir/opcodes.inc +++ b/src/shader_recompiler/ir/opcodes.inc @@ -165,18 +165,6 @@ OPCODE(CompositeInsertU32x4, U32x4, U32x OPCODE(CompositeShuffleU32x2, U32x2, U32x2, U32x2, U32, U32, ) OPCODE(CompositeShuffleU32x3, U32x3, U32x3, U32x3, U32, U32, U32, ) OPCODE(CompositeShuffleU32x4, U32x4, U32x4, U32x4, U32, U32, U32, U32, ) -OPCODE(CompositeConstructF16x2, F16x2, F16, F16, ) -OPCODE(CompositeConstructF16x3, F16x3, F16, F16, F16, ) -OPCODE(CompositeConstructF16x4, F16x4, F16, F16, F16, F16, ) -OPCODE(CompositeExtractF16x2, F16, F16x2, U32, ) -OPCODE(CompositeExtractF16x3, F16, F16x3, U32, ) -OPCODE(CompositeExtractF16x4, F16, F16x4, U32, ) -OPCODE(CompositeInsertF16x2, F16x2, F16x2, F16, U32, ) -OPCODE(CompositeInsertF16x3, F16x3, F16x3, F16, U32, ) -OPCODE(CompositeInsertF16x4, F16x4, F16x4, F16, U32, ) -OPCODE(CompositeShuffleF16x2, F16x2, F16x2, F16x2, U32, U32, ) -OPCODE(CompositeShuffleF16x3, F16x3, F16x3, F16x3, U32, U32, U32, ) -OPCODE(CompositeShuffleF16x4, F16x4, F16x4, F16x4, U32, U32, U32, U32, ) OPCODE(CompositeConstructF32x2, F32x2, F32, F32, ) OPCODE(CompositeConstructF32x3, F32x3, F32, F32, F32, ) OPCODE(CompositeConstructF32x4, F32x4, F32, F32, F32, F32, ) @@ -190,27 +178,11 @@ OPCODE(CompositeInsertF32x4, F32x4, F32x OPCODE(CompositeShuffleF32x2, F32x2, F32x2, F32x2, U32, U32, ) OPCODE(CompositeShuffleF32x3, F32x3, F32x3, F32x3, U32, U32, U32, ) OPCODE(CompositeShuffleF32x4, F32x4, F32x4, F32x4, U32, U32, U32, U32, ) -OPCODE(CompositeConstructF64x2, F64x2, F64, F64, ) -OPCODE(CompositeConstructF64x3, F64x3, F64, F64, F64, ) -OPCODE(CompositeConstructF64x4, F64x4, F64, F64, F64, F64, ) -OPCODE(CompositeExtractF64x2, F64, F64x2, U32, ) -OPCODE(CompositeExtractF64x3, F64, F64x3, U32, ) -OPCODE(CompositeExtractF64x4, F64, F64x4, U32, ) -OPCODE(CompositeInsertF64x2, F64x2, F64x2, F64, U32, ) -OPCODE(CompositeInsertF64x3, F64x3, F64x3, F64, U32, ) -OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, ) -OPCODE(CompositeShuffleF64x2, F64x2, F64x2, F64x2, U32, U32, ) -OPCODE(CompositeShuffleF64x3, F64x3, F64x3, F64x3, U32, U32, U32, ) -OPCODE(CompositeShuffleF64x4, F64x4, F64x4, F64x4, U32, U32, U32, U32, ) // Select operations OPCODE(SelectU1, U1, U1, U1, U1, ) -OPCODE(SelectU8, U8, U1, U8, U8, ) -OPCODE(SelectU16, U16, U1, U16, U16, ) OPCODE(SelectU32, U32, U1, U32, U32, ) -OPCODE(SelectU64, U64, U1, U64, U64, ) OPCODE(SelectF32, F32, U1, F32, F32, ) -OPCODE(SelectF64, F64, U1, F64, F64, ) // Bitwise conversions OPCODE(BitCastU16F16, U16, F16, ) diff --git a/src/shader_recompiler/ir/passes/constant_propagation_pass.cpp b/src/shader_recompiler/ir/passes/constant_propagation_pass.cpp index 5f9a3cc55..69d8fdd99 100644 --- a/src/shader_recompiler/ir/passes/constant_propagation_pass.cpp +++ b/src/shader_recompiler/ir/passes/constant_propagation_pass.cpp @@ -403,12 +403,8 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) { case IR::Opcode::UnpackSint2_10_10_10: return FoldInverseFunc(inst, IR::Opcode::PackSint2_10_10_10); case IR::Opcode::SelectU1: - case IR::Opcode::SelectU8: - case IR::Opcode::SelectU16: case IR::Opcode::SelectU32: - case IR::Opcode::SelectU64: case IR::Opcode::SelectF32: - case IR::Opcode::SelectF64: return FoldSelect(inst); case IR::Opcode::FPNeg32: FoldWhenAllImmediates(inst, [](f32 a) { return -a; }); @@ -563,15 +559,6 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) { case IR::Opcode::CompositeExtractF32x4: return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF32x4, IR::Opcode::CompositeInsertF32x4); - case IR::Opcode::CompositeExtractF16x2: - return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x2, - IR::Opcode::CompositeInsertF16x2); - case IR::Opcode::CompositeExtractF16x3: - return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x3, - IR::Opcode::CompositeInsertF16x3); - case IR::Opcode::CompositeExtractF16x4: - return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x4, - IR::Opcode::CompositeInsertF16x4); case IR::Opcode::ConvertF32F16: return FoldConvert(inst, IR::Opcode::ConvertF16F32); case IR::Opcode::ConvertF16F32: diff --git a/src/shader_recompiler/ir/passes/lower_fp64_to_fp32.cpp b/src/shader_recompiler/ir/passes/lower_fp64_to_fp32.cpp index 3c30e75b4..623c0f924 100644 --- a/src/shader_recompiler/ir/passes/lower_fp64_to_fp32.cpp +++ b/src/shader_recompiler/ir/passes/lower_fp64_to_fp32.cpp @@ -50,32 +50,6 @@ IR::Value F32ToPackedF64(IR::IREmitter& ir, const IR::Value& raw) { static IR::Opcode Replace(IR::Opcode op) { switch (op) { - case IR::Opcode::CompositeConstructF64x2: - return IR::Opcode::CompositeConstructF32x2; - case IR::Opcode::CompositeConstructF64x3: - return IR::Opcode::CompositeConstructF32x3; - case IR::Opcode::CompositeConstructF64x4: - return IR::Opcode::CompositeConstructF32x4; - case IR::Opcode::CompositeExtractF64x2: - return IR::Opcode::CompositeExtractF32x2; - case IR::Opcode::CompositeExtractF64x3: - return IR::Opcode::CompositeExtractF32x3; - case IR::Opcode::CompositeExtractF64x4: - return IR::Opcode::CompositeExtractF32x4; - case IR::Opcode::CompositeInsertF64x2: - return IR::Opcode::CompositeInsertF32x2; - case IR::Opcode::CompositeInsertF64x3: - return IR::Opcode::CompositeInsertF32x3; - case IR::Opcode::CompositeInsertF64x4: - return IR::Opcode::CompositeInsertF32x4; - case IR::Opcode::CompositeShuffleF64x2: - return IR::Opcode::CompositeShuffleF32x2; - case IR::Opcode::CompositeShuffleF64x3: - return IR::Opcode::CompositeShuffleF32x3; - case IR::Opcode::CompositeShuffleF64x4: - return IR::Opcode::CompositeShuffleF32x4; - case IR::Opcode::SelectF64: - return IR::Opcode::SelectF64; case IR::Opcode::FPAbs64: return IR::Opcode::FPAbs32; case IR::Opcode::FPAdd64: diff --git a/src/shader_recompiler/ir/passes/shader_info_collection_pass.cpp b/src/shader_recompiler/ir/passes/shader_info_collection_pass.cpp index 8f0e61da2..faae52c8f 100644 --- a/src/shader_recompiler/ir/passes/shader_info_collection_pass.cpp +++ b/src/shader_recompiler/ir/passes/shader_info_collection_pass.cpp @@ -73,6 +73,7 @@ void Visit(Info& info, const IR::Inst& inst) { break; case IR::Opcode::ConvertF16F32: case IR::Opcode::ConvertF32F16: + case IR::Opcode::BitCastU16F16: case IR::Opcode::BitCastF16U16: info.uses_fp16 = true; break; diff --git a/src/shader_recompiler/profile.h b/src/shader_recompiler/profile.h index ba6facff5..c51e00088 100644 --- a/src/shader_recompiler/profile.h +++ b/src/shader_recompiler/profile.h @@ -13,6 +13,7 @@ struct Profile { bool support_int8{}; bool support_int16{}; bool support_int64{}; + bool support_float16{}; bool support_float64{}; bool support_fp32_denorm_preserve{}; bool support_fp32_denorm_flush{}; diff --git a/src/video_core/renderer_vulkan/vk_instance.h b/src/video_core/renderer_vulkan/vk_instance.h index 09f68d764..d7d434e54 100644 --- a/src/video_core/renderer_vulkan/vk_instance.h +++ b/src/video_core/renderer_vulkan/vk_instance.h @@ -89,6 +89,11 @@ public: return features.depthBounds; } + /// Returns true if 16-bit floats are supported in shaders + bool IsShaderFloat16Supported() const { + return vk12_features.shaderFloat16; + } + /// Returns true if 64-bit floats are supported in shaders bool IsShaderFloat64Supported() const { return features.shaderFloat64; diff --git a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp index 37623bb32..994184cf1 100644 --- a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp +++ b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp @@ -230,6 +230,7 @@ PipelineCache::PipelineCache(const Instance& instance_, Scheduler& scheduler_, .support_int8 = instance.IsShaderInt8Supported(), .support_int16 = instance.IsShaderInt16Supported(), .support_int64 = instance.IsShaderInt64Supported(), + .support_float16 = instance.IsShaderFloat16Supported(), .support_float64 = instance.IsShaderFloat64Supported(), .support_fp32_denorm_preserve = bool(vk12_props.shaderDenormPreserveFloat32), .support_fp32_denorm_flush = bool(vk12_props.shaderDenormFlushToZeroFloat32),