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https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-03 07:52:31 +00:00
fix runtime info after rebase
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parent
a24945b952
commit
0f6d75b421
@ -1003,7 +1003,7 @@ void Translator::V_FFBH_U32(const GcnInst& inst) {
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IR::U32 Translator::VMovRelSHelper(u32 src_vgprno, const IR::U32 m0) {
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IR::U32 Translator::VMovRelSHelper(u32 src_vgprno, const IR::U32 m0) {
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// Read from VGPR0 by default when src_vgprno + m0 > num_allocated_vgprs
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// Read from VGPR0 by default when src_vgprno + m0 > num_allocated_vgprs
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IR::U32 src_val = ir.GetVectorReg<IR::U32>(IR::VectorReg::V0);
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IR::U32 src_val = ir.GetVectorReg<IR::U32>(IR::VectorReg::V0);
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for (u32 i = src_vgprno; i < info.num_allocated_vgprs; i++) {
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for (u32 i = src_vgprno; i < runtime_info.num_allocated_vgprs; i++) {
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const IR::U1 cond = ir.IEqual(m0, ir.Imm32(i - src_vgprno));
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const IR::U1 cond = ir.IEqual(m0, ir.Imm32(i - src_vgprno));
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src_val =
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src_val =
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IR::U32{ir.Select(cond, ir.GetVectorReg<IR::U32>(IR::VectorReg::V0 + i), src_val)};
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IR::U32{ir.Select(cond, ir.GetVectorReg<IR::U32>(IR::VectorReg::V0 + i), src_val)};
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@ -1012,7 +1012,7 @@ IR::U32 Translator::VMovRelSHelper(u32 src_vgprno, const IR::U32 m0) {
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}
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}
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void Translator::VMovRelDHelper(u32 dst_vgprno, const IR::U32 src_val, const IR::U32 m0) {
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void Translator::VMovRelDHelper(u32 dst_vgprno, const IR::U32 src_val, const IR::U32 m0) {
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for (u32 i = dst_vgprno; i < info.num_allocated_vgprs; i++) {
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for (u32 i = dst_vgprno; i < runtime_info.num_allocated_vgprs; i++) {
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const IR::U1 cond = ir.IEqual(m0, ir.Imm32(i - dst_vgprno));
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const IR::U1 cond = ir.IEqual(m0, ir.Imm32(i - dst_vgprno));
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const IR::U32 dst_val =
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const IR::U32 dst_val =
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IR::U32{ir.Select(cond, src_val, ir.GetVectorReg<IR::U32>(IR::VectorReg::V0 + i))};
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IR::U32{ir.Select(cond, src_val, ir.GetVectorReg<IR::U32>(IR::VectorReg::V0 + i))};
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@ -76,6 +76,7 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
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case Shader::Stage::Vertex: {
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case Shader::Stage::Vertex: {
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info.num_user_data = regs.vs_program.settings.num_user_regs;
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info.num_user_data = regs.vs_program.settings.num_user_regs;
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info.num_input_vgprs = regs.vs_program.settings.vgpr_comp_cnt;
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info.num_input_vgprs = regs.vs_program.settings.vgpr_comp_cnt;
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info.num_allocated_vgprs = regs.vs_program.settings.num_vgprs * 4;
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GatherVertexOutputs(info.vs_info, regs.vs_output_control);
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GatherVertexOutputs(info.vs_info, regs.vs_output_control);
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info.vs_info.emulate_depth_negative_one_to_one =
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info.vs_info.emulate_depth_negative_one_to_one =
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!instance.IsDepthClipControlSupported() &&
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!instance.IsDepthClipControlSupported() &&
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@ -84,6 +85,7 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
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}
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}
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case Shader::Stage::Fragment: {
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case Shader::Stage::Fragment: {
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info.num_user_data = regs.ps_program.settings.num_user_regs;
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info.num_user_data = regs.ps_program.settings.num_user_regs;
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info.num_allocated_vgprs = regs.ps_program.settings.num_vgprs * 4;
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std::ranges::transform(graphics_key.mrt_swizzles, info.fs_info.mrt_swizzles.begin(),
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std::ranges::transform(graphics_key.mrt_swizzles, info.fs_info.mrt_swizzles.begin(),
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[](Liverpool::ColorBuffer::SwapMode mode) {
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[](Liverpool::ColorBuffer::SwapMode mode) {
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return static_cast<Shader::MrtSwizzle>(mode);
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return static_cast<Shader::MrtSwizzle>(mode);
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@ -102,6 +104,7 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
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case Shader::Stage::Compute: {
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case Shader::Stage::Compute: {
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const auto& cs_pgm = regs.cs_program;
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const auto& cs_pgm = regs.cs_program;
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info.num_user_data = cs_pgm.settings.num_user_regs;
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info.num_user_data = cs_pgm.settings.num_user_regs;
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info.num_allocated_vgprs = regs.cs_program.settings.num_vgprs * 4;
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info.cs_info.workgroup_size = {cs_pgm.num_thread_x.full, cs_pgm.num_thread_y.full,
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info.cs_info.workgroup_size = {cs_pgm.num_thread_x.full, cs_pgm.num_thread_y.full,
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cs_pgm.num_thread_z.full};
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cs_pgm.num_thread_z.full};
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info.cs_info.tgid_enable = {cs_pgm.IsTgidEnabled(0), cs_pgm.IsTgidEnabled(1),
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info.cs_info.tgid_enable = {cs_pgm.IsTgidEnabled(0), cs_pgm.IsTgidEnabled(1),
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