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shader translate: fix overflow detection in V_ADD_I32
use vcc lo instead of vcc thread bit
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@ -97,19 +97,23 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
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const auto src0 = GetSrc<IR::U32>(inst.src[0]);
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const auto src0 = GetSrc<IR::U32>(inst.src[0]);
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const auto src1 = GetSrc<IR::U32>(inst.src[1]);
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const auto src1 = GetSrc<IR::U32>(inst.src[1]);
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IR::U1 scarry;
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IR::U32 scarry;
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if (inst.src_count == 3) { // VOP3
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if (inst.src_count == 3) { // VOP3
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scarry = ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[2].code));
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IR::U1 thread_bit{ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[2].code))};
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scarry = IR::U32{ir.Select(thread_bit, ir.Imm32(1), ir.Imm32(0))};
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} else { // VOP2
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} else { // VOP2
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scarry = ir.GetVcc();
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scarry = ir.GetVccLo();
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}
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}
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const IR::U32 carry_v{ir.Select(scarry, ir.Imm32(1), ir.Imm32(0))};
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IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), scarry);
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IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), carry_v);
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const IR::VectorReg dst_reg{inst.dst[0].code};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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ir.SetVectorReg(dst_reg, result);
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ir.SetVectorReg(dst_reg, result);
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ir.SetVcc(ir.IGreaterThan(result, ir.Imm32(0xFFFFFFFF), false));
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IR::U1 less_src0 = ir.ILessThan(result, src0, false);
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IR::U1 less_src1 = ir.ILessThan(result, src1, false);
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IR::U1 did_overflow = ir.LogicalOr(less_src0, less_src1);
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ir.SetVcc(did_overflow);
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}
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}
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void Translator::V_CVT_F32_I32(const GcnInst& inst) {
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void Translator::V_CVT_F32_I32(const GcnInst& inst) {
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