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buffer_atomic_imax_x2 (#3130)
* buffer_atomic_imax_x2 * Define Int64Atomics SPIR-V capability
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@@ -511,8 +511,16 @@ Value IREmitter::BufferAtomicFMin(const Value& handle, const Value& address, con
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Value IREmitter::BufferAtomicIMax(const Value& handle, const Value& address, const Value& value,
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bool is_signed, BufferInstInfo info) {
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return is_signed ? Inst(Opcode::BufferAtomicSMax32, Flags{info}, handle, address, value)
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: Inst(Opcode::BufferAtomicUMax32, Flags{info}, handle, address, value);
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switch (value.Type()) {
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case Type::U32:
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return is_signed ? Inst(Opcode::BufferAtomicSMax32, Flags{info}, handle, address, value)
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: Inst(Opcode::BufferAtomicUMax32, Flags{info}, handle, address, value);
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case Type::U64:
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return is_signed ? Inst(Opcode::BufferAtomicSMax64, Flags{info}, handle, address, value)
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: Inst(Opcode::BufferAtomicUMax64, Flags{info}, handle, address, value);
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default:
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ThrowInvalidType(value.Type());
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}
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}
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Value IREmitter::BufferAtomicFMax(const Value& handle, const Value& address, const Value& value,
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@@ -73,7 +73,9 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::BufferAtomicUMin32:
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case Opcode::BufferAtomicFMin32:
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case Opcode::BufferAtomicSMax32:
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case Opcode::BufferAtomicSMax64:
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case Opcode::BufferAtomicUMax32:
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case Opcode::BufferAtomicUMax64:
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case Opcode::BufferAtomicFMax32:
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case Opcode::BufferAtomicInc32:
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case Opcode::BufferAtomicDec32:
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@@ -127,7 +127,9 @@ OPCODE(BufferAtomicSMin32, U32, Opaq
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OPCODE(BufferAtomicUMin32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicFMin32, U32, Opaque, Opaque, F32 )
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OPCODE(BufferAtomicSMax32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicSMax64, U64, Opaque, Opaque, U64 )
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OPCODE(BufferAtomicUMax32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicUMax64, U64, Opaque, Opaque, U64 )
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OPCODE(BufferAtomicFMax32, U32, Opaque, Opaque, F32 )
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OPCODE(BufferAtomicInc32, U32, Opaque, Opaque, )
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OPCODE(BufferAtomicDec32, U32, Opaque, Opaque, )
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@@ -23,7 +23,9 @@ bool IsBufferAtomic(const IR::Inst& inst) {
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case IR::Opcode::BufferAtomicUMin32:
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case IR::Opcode::BufferAtomicFMin32:
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case IR::Opcode::BufferAtomicSMax32:
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case IR::Opcode::BufferAtomicSMax64:
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case IR::Opcode::BufferAtomicUMax32:
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case IR::Opcode::BufferAtomicUMax64:
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case IR::Opcode::BufferAtomicFMax32:
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case IR::Opcode::BufferAtomicInc32:
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case IR::Opcode::BufferAtomicDec32:
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@@ -53,9 +53,11 @@ void Visit(Info& info, const IR::Inst& inst) {
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case IR::Opcode::SharedAtomicXor32:
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info.shared_types |= IR::Type::U32;
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break;
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case IR::Opcode::SharedAtomicIAdd64:
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info.uses_shared_int64_atomics = true;
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[[fallthrough]];
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case IR::Opcode::LoadSharedU64:
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case IR::Opcode::WriteSharedU64:
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case IR::Opcode::SharedAtomicIAdd64:
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info.shared_types |= IR::Type::U64;
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break;
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case IR::Opcode::ConvertF16F32:
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@@ -98,6 +100,11 @@ void Visit(Info& info, const IR::Inst& inst) {
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case IR::Opcode::BufferAtomicFMin32:
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info.uses_buffer_atomic_float_min_max = true;
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break;
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case IR::Opcode::BufferAtomicIAdd64:
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case IR::Opcode::BufferAtomicSMax64:
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case IR::Opcode::BufferAtomicUMax64:
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info.uses_buffer_int64_atomics = true;
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break;
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case IR::Opcode::LaneId:
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info.uses_lane_id = true;
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break;
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