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shader recompiler: removed automatic conversion to force_flt in GetSRc
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c73aff3f8d
commit
21ce67e8a0
@ -77,20 +77,19 @@ void Translator::EmitPrologue() {
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template <>
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template <>
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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// Input modifiers work on float values.
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force_flt |= operand.input_modifier.abs | operand.input_modifier.neg;
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IR::U32F32 value{};
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IR::U32F32 value{};
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bool is_float = operand.type == ScalarType::Float32 || force_flt;
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switch (operand.field) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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if (is_float) {
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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} else {
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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}
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break;
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break;
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case OperandField::VectorGPR:
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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if (is_float) {
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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} else {
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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@ -164,12 +163,14 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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UNREACHABLE();
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UNREACHABLE();
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}
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}
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if (is_float) {
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if (operand.input_modifier.abs) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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value = ir.FPAbs(value);
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}
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}
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if (operand.input_modifier.neg) {
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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value = ir.FPNeg(value);
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}
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}
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}
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return value;
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return value;
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}
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}
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@ -185,13 +186,12 @@ IR::F32 Translator::GetSrc(const InstOperand& operand, bool) {
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template <>
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template <>
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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// Input modifiers work on float values.
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force_flt |= operand.input_modifier.abs | operand.input_modifier.neg;
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IR::U64F64 value{};
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IR::U64F64 value{};
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bool is_float = operand.type == ScalarType::Float64 || force_flt;
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switch (operand.field) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float64 || force_flt) {
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if (is_float) {
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value = ir.GetScalarReg<IR::F64>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::F64>(IR::ScalarReg(operand.code));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value = ir.GetScalarReg<IR::U64>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::U64>(IR::ScalarReg(operand.code));
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@ -200,7 +200,7 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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}
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}
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break;
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break;
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case OperandField::VectorGPR:
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float64 || force_flt) {
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if (is_float) {
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value = ir.GetVectorReg<IR::F64>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::F64>(IR::VectorReg(operand.code));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value = ir.GetVectorReg<IR::U64>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::U64>(IR::VectorReg(operand.code));
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@ -276,12 +276,14 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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UNREACHABLE();
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UNREACHABLE();
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}
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}
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if (is_float) {
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if (operand.input_modifier.abs) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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value = ir.FPAbs(value);
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}
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}
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if (operand.input_modifier.neg) {
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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value = ir.FPNeg(value);
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}
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}
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}
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return value;
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return value;
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}
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}
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