mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-01 15:02:40 +00:00
Copy context get set
This commit is contained in:
Lander Gallastegi
Lander Gallastegi
parent
35d3ee8ecd
commit
2584ec2d76
@ -903,6 +903,7 @@ if (ARCHITECTURE STREQUAL "x86_64")
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src/shader_recompiler/backend/asm_x64/emit_x64_barrier.cpp
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src/shader_recompiler/backend/asm_x64/emit_x64_bitwise_conversion.cpp
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src/shader_recompiler/backend/asm_x64/emit_x64_composite.cpp
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src/shader_recompiler/backend/asm_x64/emit_x64_context_get_set.cpp
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src/shader_recompiler/backend/asm_x64/emit_x64_image.cpp
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src/shader_recompiler/backend/asm_x64/emit_x64_instructions.h
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src/shader_recompiler/backend/asm_x64/emit_x64_shared_memory.cpp
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@ -0,0 +1,537 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/backend/asm_x64/x64_emit_context.h"
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namespace Shader::Backend::X64 {
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using namespace Xbyak;
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using namespace Xbyak::util;
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Id EmitGetUserData(EmitContext& ctx, IR::ScalarReg reg) {
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const u32 index = ctx.binding.user_data + ctx.info.ud_mask.Index(reg);
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const u32 half = PushData::UdRegsIndex + (index >> 2);
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const Id ud_ptr{ctx.OpAccessChain(ctx.TypePointer(spv::StorageClass::PushConstant, ctx.U32[1]),
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ctx.push_data_block, ctx.ConstU32(half),
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ctx.ConstU32(index & 3))};
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const Id ud_reg{ctx.OpLoad(ctx.U32[1], ud_ptr)};
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ctx.Name(ud_reg, fmt::format("ud_{}", u32(reg)));
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return ud_reg;
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}
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void EmitSetUserData(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetThreadBitScalarReg(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetThreadBitScalarReg(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetScalarRegister(EmitContext&) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetScalarRegister(EmitContext&) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetVectorRegister(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetVectorRegister(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetGotoVariable(EmitContext&) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetGotoVariable(EmitContext&) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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using BufferAlias = EmitContext::BufferAlias;
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Id EmitReadConst(EmitContext& ctx, IR::Inst* inst) {
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const auto& srt_flatbuf = ctx.buffers.back();
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ASSERT(srt_flatbuf.binding >= 0 && srt_flatbuf.buffer_type == BufferType::ReadConstUbo);
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const auto [id, pointer_type] = srt_flatbuf[BufferAlias::U32];
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, ctx.Def(inst->Arg(1)))};
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return ctx.OpLoad(ctx.U32[1], ptr);
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}
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Id EmitReadConstBuffer(EmitContext& ctx, u32 handle, Id index) {
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const auto& buffer = ctx.buffers[handle];
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index = ctx.OpIAdd(ctx.U32[1], index, buffer.offset_dwords);
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const auto [id, pointer_type] = buffer[BufferAlias::U32];
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index)};
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const Id result{ctx.OpLoad(ctx.U32[1], ptr)};
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if (Sirit::ValidId(buffer.size_dwords)) {
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], index, buffer.size_dwords);
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return ctx.OpSelect(ctx.U32[1], in_bounds, result, ctx.u32_zero_value);
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} else {
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return result;
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}
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}
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Id EmitReadStepRate(EmitContext& ctx, int rate_idx) {
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const auto index{rate_idx == 0 ? PushData::Step0Index : PushData::Step1Index};
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return ctx.OpLoad(
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ctx.U32[1], ctx.OpAccessChain(ctx.TypePointer(spv::StorageClass::PushConstant, ctx.U32[1]),
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ctx.push_data_block, ctx.ConstU32(index)));
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}
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static Id EmitGetAttributeForGeometry(EmitContext& ctx, IR::Attribute attr, u32 comp, Id index) {
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if (IR::IsPosition(attr)) {
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ASSERT(attr == IR::Attribute::Position0);
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const auto position_arr_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[4]);
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const auto pointer{ctx.OpAccessChain(position_arr_ptr, ctx.gl_in, index, ctx.ConstU32(0u))};
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const auto position_comp_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(position_comp_ptr, pointer, ctx.ConstU32(comp)));
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}
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if (IR::IsParam(attr)) {
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const u32 param_id{u32(attr) - u32(IR::Attribute::Param0)};
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const auto param = ctx.input_params.at(param_id).id;
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const auto param_arr_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[4]);
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const auto pointer{ctx.OpAccessChain(param_arr_ptr, param, index)};
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const auto position_comp_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(position_comp_ptr, pointer, ctx.ConstU32(comp)));
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}
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UNREACHABLE();
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp, Id index) {
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if (ctx.info.l_stage == LogicalStage::Geometry) {
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return EmitGetAttributeForGeometry(ctx, attr, comp, index);
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} else if (ctx.info.l_stage == LogicalStage::TessellationControl ||
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ctx.info.l_stage == LogicalStage::TessellationEval) {
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if (IR::IsTessCoord(attr)) {
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const u32 component = attr == IR::Attribute::TessellationEvaluationPointU ? 0 : 1;
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const auto component_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[1]);
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const auto pointer{
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ctx.OpAccessChain(component_ptr, ctx.tess_coord, ctx.ConstU32(component))};
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return ctx.OpLoad(ctx.F32[1], pointer);
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}
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UNREACHABLE();
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}
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& param{ctx.input_params.at(index)};
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if (param.buffer_handle >= 0) {
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const auto step_rate = EmitReadStepRate(ctx, param.id.value);
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const auto offset = ctx.OpIAdd(
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ctx.U32[1],
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ctx.OpIMul(
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ctx.U32[1],
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ctx.OpUDiv(ctx.U32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_id), step_rate),
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ctx.ConstU32(param.num_components)),
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ctx.ConstU32(comp));
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return EmitReadConstBuffer(ctx, param.buffer_handle, offset);
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}
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Id result;
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if (param.is_loaded) {
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// Attribute is either default or manually interpolated. The id points to an already
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// loaded vector.
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result = ctx.OpCompositeExtract(param.component_type, param.id, comp);
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} else if (param.num_components > 1) {
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// Attribute is a vector and we need to access a specific component.
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const Id pointer{ctx.OpAccessChain(param.pointer_type, param.id, ctx.ConstU32(comp))};
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result = ctx.OpLoad(param.component_type, pointer);
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} else {
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// Attribute is a single float or interger, simply load it.
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result = ctx.OpLoad(param.component_type, param.id);
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}
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if (param.is_integer) {
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result = ctx.OpBitcast(ctx.F32[1], result);
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}
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return result;
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}
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switch (attr) {
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case IR::Attribute::FragCoord: {
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const Id coord = ctx.OpLoad(
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ctx.F32[1], ctx.OpAccessChain(ctx.input_f32, ctx.frag_coord, ctx.ConstU32(comp)));
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if (comp == 3) {
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return ctx.OpFDiv(ctx.F32[1], ctx.ConstF32(1.f), coord);
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}
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return coord;
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}
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case IR::Attribute::TessellationEvaluationPointU:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.tess_coord, ctx.u32_zero_value));
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case IR::Attribute::TessellationEvaluationPointV:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.tess_coord, ctx.ConstU32(1U)));
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default:
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UNREACHABLE_MSG("Read attribute {}", attr);
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}
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}
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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switch (attr) {
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case IR::Attribute::VertexId:
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_index);
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case IR::Attribute::InstanceId:
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return ctx.OpLoad(ctx.U32[1], ctx.instance_id);
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case IR::Attribute::InstanceId0:
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return EmitReadStepRate(ctx, 0);
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case IR::Attribute::InstanceId1:
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return EmitReadStepRate(ctx, 1);
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case IR::Attribute::WorkgroupIndex:
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return ctx.workgroup_index_id;
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case IR::Attribute::WorkgroupId:
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return ctx.OpCompositeExtract(ctx.U32[1], ctx.OpLoad(ctx.U32[3], ctx.workgroup_id), comp);
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case IR::Attribute::LocalInvocationId:
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return ctx.OpCompositeExtract(ctx.U32[1], ctx.OpLoad(ctx.U32[3], ctx.local_invocation_id),
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comp);
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case IR::Attribute::IsFrontFace:
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return ctx.OpSelect(ctx.U32[1], ctx.OpLoad(ctx.U1[1], ctx.front_facing), ctx.u32_one_value,
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ctx.u32_zero_value);
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case IR::Attribute::PrimitiveId:
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return ctx.OpLoad(ctx.U32[1], ctx.primitive_id);
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case IR::Attribute::InvocationId:
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ASSERT(ctx.info.l_stage == LogicalStage::Geometry ||
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ctx.info.l_stage == LogicalStage::TessellationControl);
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return ctx.OpLoad(ctx.U32[1], ctx.invocation_id);
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case IR::Attribute::PatchVertices:
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ASSERT(ctx.info.l_stage == LogicalStage::TessellationControl);
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return ctx.OpLoad(ctx.U32[1], ctx.patch_vertices);
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case IR::Attribute::PackedHullInvocationInfo: {
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ASSERT(ctx.info.l_stage == LogicalStage::TessellationControl);
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// [0:8]: patch id within VGT
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// [8:12]: output control point id
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// But 0:8 should be treated as 0 for attribute addressing purposes
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if (ctx.runtime_info.hs_info.IsPassthrough()) {
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// Gcn shader would run with 1 thread, but we need to run a thread for
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// each output control point.
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// If Gcn shader uses this value, we should make sure all threads in the
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// Vulkan shader use 0
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return ctx.ConstU32(0u);
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} else {
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const Id invocation_id = ctx.OpLoad(ctx.U32[1], ctx.invocation_id);
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return ctx.OpShiftLeftLogical(ctx.U32[1], invocation_id, ctx.ConstU32(8u));
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}
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}
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default:
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UNREACHABLE_MSG("Read U32 attribute {}", attr);
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}
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}
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 element) {
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if (attr == IR::Attribute::Position1) {
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LOG_WARNING(Render_Vulkan, "Ignoring pos1 export");
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return;
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}
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const Id pointer{OutputAttrPointer(ctx, attr, element)};
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const auto component_type{OutputAttrComponentType(ctx, attr)};
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if (component_type.second) {
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ctx.OpStore(pointer, ctx.OpBitcast(component_type.first, value));
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} else {
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ctx.OpStore(pointer, value);
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}
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}
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Id EmitGetTessGenericAttribute(EmitContext& ctx, Id vertex_index, Id attr_index, Id comp_index) {
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const auto attr_comp_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1], ctx.OpAccessChain(attr_comp_ptr, ctx.input_attr_array,
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vertex_index, attr_index, comp_index));
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}
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Id EmitReadTcsGenericOuputAttribute(EmitContext& ctx, Id vertex_index, Id attr_index,
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Id comp_index) {
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const auto attr_comp_ptr = ctx.TypePointer(spv::StorageClass::Output, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1], ctx.OpAccessChain(attr_comp_ptr, ctx.output_attr_array,
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vertex_index, attr_index, comp_index));
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}
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void EmitSetTcsGenericAttribute(EmitContext& ctx, Id value, Id attr_index, Id comp_index) {
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// Implied vertex index is invocation_id
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const auto component_ptr = ctx.TypePointer(spv::StorageClass::Output, ctx.F32[1]);
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Id pointer =
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ctx.OpAccessChain(component_ptr, ctx.output_attr_array,
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ctx.OpLoad(ctx.U32[1], ctx.invocation_id), attr_index, comp_index);
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ctx.OpStore(pointer, value);
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}
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Id EmitGetPatch(EmitContext& ctx, IR::Patch patch) {
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const u32 index{IR::GenericPatchIndex(patch)};
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const Id element{ctx.ConstU32(IR::GenericPatchElement(patch))};
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const Id type{ctx.l_stage == LogicalStage::TessellationControl ? ctx.output_f32
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: ctx.input_f32};
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const Id pointer{ctx.OpAccessChain(type, ctx.patches.at(index), element)};
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return ctx.OpLoad(ctx.F32[1], pointer);
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}
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void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value) {
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const Id pointer{[&] {
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if (IR::IsGeneric(patch)) {
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const u32 index{IR::GenericPatchIndex(patch)};
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const Id element{ctx.ConstU32(IR::GenericPatchElement(patch))};
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return ctx.OpAccessChain(ctx.output_f32, ctx.patches.at(index), element);
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}
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switch (patch) {
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case IR::Patch::TessellationLodLeft:
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case IR::Patch::TessellationLodRight:
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case IR::Patch::TessellationLodTop:
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case IR::Patch::TessellationLodBottom: {
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const u32 index{static_cast<u32>(patch) - u32(IR::Patch::TessellationLodLeft)};
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const Id index_id{ctx.ConstU32(index)};
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return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_outer, index_id);
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}
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case IR::Patch::TessellationLodInteriorU:
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return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_inner,
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ctx.u32_zero_value);
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case IR::Patch::TessellationLodInteriorV:
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return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_inner, ctx.ConstU32(1u));
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default:
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UNREACHABLE_MSG("Patch {}", u32(patch));
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}
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}()};
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ctx.OpStore(pointer, value);
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}
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template <u32 N>
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static Id EmitLoadBufferBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, Id result,
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bool is_float) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a select.
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const auto result_type = is_float ? ctx.F32[N] : ctx.U32[N];
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auto compare_index = index;
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auto zero_value = is_float ? ctx.f32_zero_value : ctx.u32_zero_value;
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if (N > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(N - 1));
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std::array<Id, N> zero_ids;
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zero_ids.fill(zero_value);
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zero_value = ctx.ConstantComposite(result_type, zero_ids);
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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return ctx.OpSelect(result_type, in_bounds, result, zero_value);
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}
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// Bounds checking not enabled, just return the plain value.
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return result;
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}
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template <u32 N, BufferAlias alias>
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static Id EmitLoadBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto flags = inst->Flags<IR::BufferInstInfo>();
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const auto& spv_buffer = ctx.buffers[handle];
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if (Sirit::ValidId(spv_buffer.offset)) {
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address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
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}
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const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
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const auto& data_types = alias == BufferAlias::U32 ? ctx.U32 : ctx.F32;
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const auto [id, pointer_type] = spv_buffer[alias];
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boost::container::static_vector<Id, N> ids;
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for (u32 i = 0; i < N; i++) {
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const Id index_i = i == 0 ? index : ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(i));
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const Id ptr_i = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index_i);
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const Id result_i = ctx.OpLoad(data_types[1], ptr_i);
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if (!flags.typed) {
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// Untyped loads have bounds checking per-component.
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ids.push_back(EmitLoadBufferBoundsCheck<1>(ctx, index_i, spv_buffer.size_dwords,
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result_i, alias == BufferAlias::F32));
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} else {
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ids.push_back(result_i);
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}
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}
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const Id result = N == 1 ? ids[0] : ctx.OpCompositeConstruct(data_types[N], ids);
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if (flags.typed) {
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// Typed loads have single bounds check for the whole load.
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return EmitLoadBufferBoundsCheck<N>(ctx, index, spv_buffer.size_dwords, result,
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alias == BufferAlias::F32);
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}
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return result;
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}
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Id EmitLoadBufferU8(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto& spv_buffer = ctx.buffers[handle];
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if (Sirit::ValidId(spv_buffer.offset)) {
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address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
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}
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const auto [id, pointer_type] = spv_buffer[BufferAlias::U8];
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, address)};
|
||||
const Id result{ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U8, ptr))};
|
||||
return EmitLoadBufferBoundsCheck<1>(ctx, address, spv_buffer.size, result, false);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferU16(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
const auto& spv_buffer = ctx.buffers[handle];
|
||||
if (Sirit::ValidId(spv_buffer.offset)) {
|
||||
address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
|
||||
}
|
||||
const auto [id, pointer_type] = spv_buffer[BufferAlias::U16];
|
||||
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(1u));
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index)};
|
||||
const Id result{ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U16, ptr))};
|
||||
return EmitLoadBufferBoundsCheck<1>(ctx, index, spv_buffer.size_shorts, result, false);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<1, BufferAlias::U32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<2, BufferAlias::U32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<3, BufferAlias::U32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<4, BufferAlias::U32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<1, BufferAlias::F32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<2, BufferAlias::F32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<3, BufferAlias::F32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
return EmitLoadBufferB32xN<4, BufferAlias::F32>(ctx, inst, handle, address);
|
||||
}
|
||||
|
||||
Id EmitLoadBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
|
||||
UNREACHABLE_MSG("SPIR-V instruction");
|
||||
}
|
||||
|
||||
template <u32 N>
|
||||
void EmitStoreBufferBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
|
||||
if (Sirit::ValidId(buffer_size)) {
|
||||
// Bounds checking enabled, wrap in a conditional branch.
|
||||
auto compare_index = index;
|
||||
if (N > 1) {
|
||||
index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(N - 1));
|
||||
}
|
||||
const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
|
||||
const Id in_bounds_label = ctx.OpLabel();
|
||||
const Id merge_label = ctx.OpLabel();
|
||||
ctx.OpSelectionMerge(merge_label, spv::SelectionControlMask::MaskNone);
|
||||
ctx.OpBranchConditional(in_bounds, in_bounds_label, merge_label);
|
||||
ctx.AddLabel(in_bounds_label);
|
||||
emit_func();
|
||||
ctx.OpBranch(merge_label);
|
||||
ctx.AddLabel(merge_label);
|
||||
return;
|
||||
}
|
||||
// Bounds checking not enabled, just perform the store.
|
||||
emit_func();
|
||||
}
|
||||
|
||||
template <u32 N, BufferAlias alias>
|
||||
static void EmitStoreBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address,
|
||||
Id value) {
|
||||
const auto flags = inst->Flags<IR::BufferInstInfo>();
|
||||
const auto& spv_buffer = ctx.buffers[handle];
|
||||
if (Sirit::ValidId(spv_buffer.offset)) {
|
||||
address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
|
||||
}
|
||||
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
|
||||
const auto& data_types = alias == BufferAlias::U32 ? ctx.U32 : ctx.F32;
|
||||
const auto [id, pointer_type] = spv_buffer[alias];
|
||||
|
||||
auto store = [&] {
|
||||
for (u32 i = 0; i < N; i++) {
|
||||
const Id index_i = i == 0 ? index : ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(i));
|
||||
const Id ptr_i = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index_i);
|
||||
const Id value_i = N == 1 ? value : ctx.OpCompositeExtract(data_types[1], value, i);
|
||||
auto store_i = [&]() { ctx.OpStore(ptr_i, value_i); };
|
||||
if (!flags.typed) {
|
||||
// Untyped stores have bounds checking per-component.
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, index_i, spv_buffer.size_dwords, store_i);
|
||||
} else {
|
||||
store_i();
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
if (flags.typed) {
|
||||
// Typed stores have single bounds check for the whole store.
|
||||
EmitStoreBufferBoundsCheck<N>(ctx, index, spv_buffer.size_dwords, store);
|
||||
} else {
|
||||
store();
|
||||
}
|
||||
}
|
||||
|
||||
void EmitStoreBufferU8(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id value) {
|
||||
const auto& spv_buffer = ctx.buffers[handle];
|
||||
if (Sirit::ValidId(spv_buffer.offset)) {
|
||||
address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
|
||||
}
|
||||
const auto [id, pointer_type] = spv_buffer[BufferAlias::U8];
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, address)};
|
||||
const Id result{ctx.OpUConvert(ctx.U8, value)};
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, address, spv_buffer.size, [&] { ctx.OpStore(ptr, result); });
|
||||
}
|
||||
|
||||
void EmitStoreBufferU16(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id value) {
|
||||
const auto& spv_buffer = ctx.buffers[handle];
|
||||
if (Sirit::ValidId(spv_buffer.offset)) {
|
||||
address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
|
||||
}
|
||||
const auto [id, pointer_type] = spv_buffer[BufferAlias::U16];
|
||||
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(1u));
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index)};
|
||||
const Id result{ctx.OpUConvert(ctx.U16, value)};
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, index, spv_buffer.size_shorts,
|
||||
[&] { ctx.OpStore(ptr, result); });
|
||||
}
|
||||
|
||||
void EmitStoreBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<1, BufferAlias::U32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<2, BufferAlias::U32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<3, BufferAlias::U32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<4, BufferAlias::U32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<1, BufferAlias::F32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<2, BufferAlias::F32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<3, BufferAlias::F32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<4, BufferAlias::F32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
UNREACHABLE_MSG("SPIR-V instruction");
|
||||
}
|
||||
|
||||
}
|
||||
@ -168,7 +168,6 @@ using BufferAlias = EmitContext::BufferAlias;
|
||||
|
||||
Id EmitReadConst(EmitContext& ctx, IR::Inst* inst) {
|
||||
const auto& srt_flatbuf = ctx.buffers.back();
|
||||
ASSERT_MSG(inst->Flags<u32>() == 1, "ReadConst was not processed by the flattening pass");
|
||||
ASSERT(srt_flatbuf.binding >= 0 && srt_flatbuf.buffer_type == BufferType::ReadConstUbo);
|
||||
const auto [id, pointer_type] = srt_flatbuf[BufferAlias::U32];
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, ctx.Def(inst->Arg(1)))};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user