From 2eee78a4645941e1042cf8f6d48e1a2325157ad0 Mon Sep 17 00:00:00 2001 From: microsoftv <6063922+microsoftv@users.noreply.github.com> Date: Sat, 17 Aug 2024 14:37:48 -0400 Subject: [PATCH] distinguish RTN opcodes --- .../frontend/translate/data_share.cpp | 30 +++++++++++++------ .../frontend/translate/translate.h | 6 ++-- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/data_share.cpp b/src/shader_recompiler/frontend/translate/data_share.cpp index 5957dc1a3..b7b5aa138 100644 --- a/src/shader_recompiler/frontend/translate/data_share.cpp +++ b/src/shader_recompiler/frontend/translate/data_share.cpp @@ -26,11 +26,17 @@ void Translator::EmitDataShare(const GcnInst& inst) { case Opcode::DS_WRITE2_B64: return DS_WRITE(64, false, true, inst); case Opcode::DS_ADD_U32: - return DS_ADD_U32(inst); + return DS_ADD_U32(inst, false); case Opcode::DS_MIN_U32: - return DS_MIN_U32(inst); + return DS_MIN_U32(inst, false); case Opcode::DS_MAX_U32: - return DS_MAX_U32(inst); + return DS_MAX_U32(inst, false); + case Opcode::DS_ADD_RTN_U32: + return DS_ADD_U32(inst, true); + case Opcode::DS_MIN_RTN_U32: + return DS_MIN_U32(inst, true); + case Opcode::DS_MAX_RTN_U32: + return DS_MAX_U32(inst, true); default: LogMissingOpcode(inst); } @@ -116,34 +122,40 @@ void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnI } } -void Translator::DS_ADD_U32(const GcnInst& inst) { +void Translator::DS_ADD_U32(const GcnInst& inst, bool rtn) { const IR::U32 addr{GetSrc(inst.src[0])}; const IR::U32 data{GetSrc(inst.src[1])}; const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0)); const IR::U32 addr_offset = ir.IAdd(addr, offset); IR::VectorReg dst_reg{inst.dst[0].code}; const IR::Value original_val = ir.SharedAtomicIAdd(addr_offset, data); - SetDst(inst.dst[0], IR::U32{original_val}); + if (rtn) { + SetDst(inst.dst[0], IR::U32{original_val}); + } } -void Translator::DS_MIN_U32(const GcnInst& inst) { +void Translator::DS_MIN_U32(const GcnInst& inst, bool rtn) { const IR::U32 addr{GetSrc(inst.src[0])}; const IR::U32 data{GetSrc(inst.src[1])}; const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0)); const IR::U32 addr_offset = ir.IAdd(addr, offset); IR::VectorReg dst_reg{inst.dst[0].code}; const IR::Value original_val = ir.SharedAtomicIMin(addr_offset, data, false); - SetDst(inst.dst[0], IR::U32{original_val}); + if (rtn) { + SetDst(inst.dst[0], IR::U32{original_val}); + } } -void Translator::DS_MAX_U32(const GcnInst& inst) { +void Translator::DS_MAX_U32(const GcnInst& inst, bool rtn) { const IR::U32 addr{GetSrc(inst.src[0])}; const IR::U32 data{GetSrc(inst.src[1])}; const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0)); const IR::U32 addr_offset = ir.IAdd(addr, offset); IR::VectorReg dst_reg{inst.dst[0].code}; const IR::Value original_val = ir.SharedAtomicIMax(addr_offset, data, false); - SetDst(inst.dst[0], IR::U32{original_val}); + if (rtn) { + SetDst(inst.dst[0], IR::U32{original_val}); + } } void Translator::S_BARRIER() { diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h index 5c7b3b714..009acabdf 100644 --- a/src/shader_recompiler/frontend/translate/translate.h +++ b/src/shader_recompiler/frontend/translate/translate.h @@ -197,9 +197,9 @@ public: void DS_SWIZZLE_B32(const GcnInst& inst); void DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst); void DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst); - void DS_MAX_U32(const GcnInst& inst); - void DS_MIN_U32(const GcnInst& inst); - void DS_ADD_U32(const GcnInst& inst); + void DS_ADD_U32(const GcnInst& inst, bool rtn); + void DS_MIN_U32(const GcnInst& inst, bool rtn); + void DS_MAX_U32(const GcnInst& inst, bool rtn); void V_READFIRSTLANE_B32(const GcnInst& inst); void V_READLANE_B32(const GcnInst& inst); void V_WRITELANE_B32(const GcnInst& inst);