From 32244c097c3b18825ccaf542a0b54e22d0df6280 Mon Sep 17 00:00:00 2001 From: squidbus <175574877+squidbus@users.noreply.github.com> Date: Fri, 29 Aug 2025 18:11:21 -0700 Subject: [PATCH] shader_recompiler: Implement V_ADD_F64 and loading 64-bit float from SGPR. (#3483) --- src/shader_recompiler/frontend/translate/translate.cpp | 2 +- src/shader_recompiler/frontend/translate/translate.h | 1 + src/shader_recompiler/frontend/translate/vector_alu.cpp | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/translate.cpp b/src/shader_recompiler/frontend/translate/translate.cpp index ad6cf5f12..00d9768b8 100644 --- a/src/shader_recompiler/frontend/translate/translate.cpp +++ b/src/shader_recompiler/frontend/translate/translate.cpp @@ -367,7 +367,7 @@ T Translator::GetSrc64(const InstOperand& operand) { const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code)); const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1)); if constexpr (is_float) { - UNREACHABLE(); + value = ir.PackDouble2x32(ir.CompositeConstruct(value_lo, value_hi)); } else { value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi)); } diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h index fbd07c887..dad2cc829 100644 --- a/src/shader_recompiler/frontend/translate/translate.h +++ b/src/shader_recompiler/frontend/translate/translate.h @@ -149,6 +149,7 @@ public: void V_READLANE_B32(const GcnInst& inst); void V_WRITELANE_B32(const GcnInst& inst); void V_ADD_F32(const GcnInst& inst); + void V_ADD_F64(const GcnInst& inst); void V_SUB_F32(const GcnInst& inst); void V_SUBREV_F32(const GcnInst& inst); void V_MUL_F32(const GcnInst& inst); diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index f8be69523..de43eb8da 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -392,6 +392,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) { return V_CVT_PK_U8_F32(inst); case Opcode::V_LSHL_B64: return V_LSHL_B64(inst); + case Opcode::V_ADD_F64: + return V_ADD_F64(inst); case Opcode::V_ALIGNBIT_B32: return V_ALIGNBIT_B32(inst); case Opcode::V_ALIGNBYTE_B32: @@ -435,6 +437,12 @@ void Translator::V_ADD_F32(const GcnInst& inst) { SetDst(inst.dst[0], ir.FPAdd(src0, src1)); } +void Translator::V_ADD_F64(const GcnInst& inst) { + const IR::F64 src0{GetSrc64(inst.src[0])}; + const IR::F64 src1{GetSrc64(inst.src[1])}; + SetDst64(inst.dst[0], ir.FPAdd(src0, src1)); +} + void Translator::V_SUB_F32(const GcnInst& inst) { const IR::F32 src0{GetSrc(inst.src[0])}; const IR::F32 src1{GetSrc(inst.src[1])};