From 3b2e20d98f036ae0f9383979710837ec4a3454b6 Mon Sep 17 00:00:00 2001 From: DanielSvoboda Date: Mon, 8 Jul 2024 11:55:08 -0300 Subject: [PATCH] adjust V_MAD_I32_I24 for bit extraction --- .../frontend/translate/vector_alu.cpp | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 876305445..0a155bdce 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -361,10 +361,10 @@ void Translator::V_BFE_U32(bool is_signed, const GcnInst& inst) { SetDst(inst.dst[0], ir.BitFieldExtract(src0, src1, src2, is_signed)); } -void Translator::V_MAD_I32_I24(const GcnInst& inst) { - const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true)}; - const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true)}; - const IR::U32 src2{GetSrc(inst.src[2])}; +void Translator::V_MAD_I32_I24(const GcnInst& inst, bool performBitExtract) { + const IR::U32 src0 = performBitExtract ? ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true) : GetSrc(inst.src[0]); + const IR::U32 src1 = performBitExtract ? ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true) : GetSrc(inst.src[1]); + const IR::U32 src2 = GetSrc(inst.src[2]); SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2)); } @@ -393,10 +393,7 @@ void Translator::V_ASHRREV_I32(const GcnInst& inst) { } void Translator::V_MAD_U32_U24(const GcnInst& inst) { - const IR::U32 src0 = ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), false); - const IR::U32 src1 = ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), false); - const IR::U32 src2 = GetSrc(inst.src[2]); - SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2)); + V_MAD_I32_I24(inst, false); } void Translator::V_RNDNE_F32(const GcnInst& inst) {