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Tessellation (#1528)
* shader_recompiler: Tessellation WIP * fix compiler errors after merge DONT MERGE set log file to /dev/null DONT MERGE linux pthread bb fix save work DONT MERGE dump ir save more work fix mistake with ES shader skip list add input patch control points dynamic state random stuff * WIP Tessellation partial implementation. Squash commits * test: make local/tcs use attr arrays * attr arrays in TCS/TES * dont define empty attr arrays * switch to special opcodes for tess tcs/tes reads and tcs writes * impl tcs/tes read attr insts * rebase fix * save some work * save work probably broken and slow * put Vertex LogicalStage after TCS and TES to fix bindings * more refactors * refactor pattern matching and optimize modulos (disabled) * enable modulo opt * copyright * rebase fixes * remove some prints * remove some stuff * Add TCS/TES support for shader patching and use LogicalStage * refactor and handle wider DS instructions * get rid of GetAttributes for special tess constants reads. Immediately replace some upon seeing readconstbuffer. Gets rid of some extra passes over IR * stop relying on GNMX HsConstants struct. Change runtime_info.hs_info and some regs * delete some more stuff * update comments for current implementation * some cleanup * uint error * more cleanup * remove patch control points dynamic state (because runtime_info already depends on it) * fix potential problem with determining passthrough --------- Co-authored-by: IndecisiveTurtle <47210458+raphaelthegreat@users.noreply.github.com>
This commit is contained in:
baggins183
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@@ -143,6 +143,13 @@ struct Liverpool {
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}
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};
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struct HsTessFactorClamp {
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// I've only seen min=0.0, max=1.0 so far.
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// TODO why is max set to 1.0? Makes no sense
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float hs_max_tess;
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float hs_min_tess;
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};
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struct ComputeProgram {
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u32 dispatch_initiator;
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u32 dim_x;
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@@ -956,6 +963,7 @@ struct Liverpool {
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enum VgtStages : u32 {
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Vs = 0u, // always enabled
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EsGs = 0xB0u,
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LsHs = 0x45u,
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};
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VgtStages raw;
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@@ -963,7 +971,8 @@ struct Liverpool {
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BitField<2, 1, u32> hs_en;
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BitField<3, 2, u32> es_en;
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BitField<5, 1, u32> gs_en;
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BitField<6, 1, u32> vs_en;
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BitField<6, 2, u32> vs_en;
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BitField<8, 1, u32> dynamic_hs;
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bool IsStageEnabled(u32 stage) const {
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switch (stage) {
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@@ -1059,6 +1068,28 @@ struct Liverpool {
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};
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};
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union LsHsConfig {
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u32 raw;
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BitField<0, 8, u32> num_patches;
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BitField<8, 6, u32> hs_input_control_points;
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BitField<14, 6, u32> hs_output_control_points;
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};
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union TessellationConfig {
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u32 raw;
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BitField<0, 2, TessellationType> type;
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BitField<2, 3, TessellationPartitioning> partitioning;
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BitField<5, 3, TessellationTopology> topology;
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};
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union TessFactorMemoryBase {
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u32 base;
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u64 MemoryBase() const {
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return static_cast<u64>(base) << 8;
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}
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};
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union Eqaa {
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u32 raw;
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BitField<0, 1, u32> max_anchor_samples;
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@@ -1109,7 +1140,7 @@ struct Liverpool {
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ShaderProgram es_program;
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INSERT_PADDING_WORDS(0x2C);
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ShaderProgram hs_program;
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INSERT_PADDING_WORDS(0x2C);
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INSERT_PADDING_WORDS(0x2D48 - 0x2d08 - 20);
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ShaderProgram ls_program;
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INSERT_PADDING_WORDS(0xA4);
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ComputeProgram cs_program;
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@@ -1176,7 +1207,9 @@ struct Liverpool {
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PolygonControl polygon_control;
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ViewportControl viewport_control;
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VsOutputControl vs_output_control;
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INSERT_PADDING_WORDS(0xA290 - 0xA207 - 1);
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INSERT_PADDING_WORDS(0xA287 - 0xA207 - 1);
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HsTessFactorClamp hs_clamp;
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INSERT_PADDING_WORDS(0xA290 - 0xA287 - 2);
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GsMode vgt_gs_mode;
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INSERT_PADDING_WORDS(1);
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ModeControl mode_control;
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@@ -1200,9 +1233,10 @@ struct Liverpool {
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BitField<0, 11, u32> vgt_gs_max_vert_out;
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INSERT_PADDING_WORDS(0xA2D5 - 0xA2CE - 1);
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ShaderStageEnable stage_enable;
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INSERT_PADDING_WORDS(1);
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LsHsConfig ls_hs_config;
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u32 vgt_gs_vert_itemsize[4];
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INSERT_PADDING_WORDS(4);
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TessellationConfig tess_config;
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INSERT_PADDING_WORDS(3);
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PolygonOffset poly_offset;
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GsInstances vgt_gs_instance_cnt;
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StreamOutConfig vgt_strmout_config;
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@@ -1216,6 +1250,8 @@ struct Liverpool {
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INSERT_PADDING_WORDS(0xC24C - 0xC243);
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u32 num_indices;
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VgtNumInstances num_instances;
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INSERT_PADDING_WORDS(0xC250 - 0xC24D - 1);
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TessFactorMemoryBase vgt_tf_memory_base;
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};
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std::array<u32, NumRegs> reg_array{};
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@@ -1431,6 +1467,7 @@ static_assert(GFX6_3D_REG_INDEX(color_control) == 0xA202);
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static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
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static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
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static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
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static_assert(GFX6_3D_REG_INDEX(hs_clamp) == 0xA287);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_mode) == 0xA290);
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static_assert(GFX6_3D_REG_INDEX(mode_control) == 0xA292);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_out_prim_type) == 0xA29B);
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@@ -1445,6 +1482,7 @@ static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_itemsize) == 0xA2AC);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_max_vert_out) == 0xA2CE);
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static_assert(GFX6_3D_REG_INDEX(stage_enable) == 0xA2D5);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_vert_itemsize[0]) == 0xA2D7);
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static_assert(GFX6_3D_REG_INDEX(tess_config) == 0xA2DB);
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static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_instance_cnt) == 0xA2E4);
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static_assert(GFX6_3D_REG_INDEX(vgt_strmout_config) == 0xA2E5);
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@@ -1456,6 +1494,7 @@ static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[7].base_address) == 0xA381);
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static_assert(GFX6_3D_REG_INDEX(primitive_type) == 0xC242);
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static_assert(GFX6_3D_REG_INDEX(num_instances) == 0xC24D);
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static_assert(GFX6_3D_REG_INDEX(vgt_tf_memory_base) == 0xc250);
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#undef GFX6_3D_REG_INDEX
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@@ -3,6 +3,8 @@
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#pragma once
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#include <string_view>
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#include <fmt/format.h>
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#include "common/types.h"
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namespace AmdGpu {
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@@ -21,6 +23,69 @@ enum class FpDenormMode : u32 {
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InOutAllow = 3,
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};
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enum class TessellationType : u32 {
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Isoline = 0,
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Triangle = 1,
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Quad = 2,
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};
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constexpr std::string_view NameOf(TessellationType type) {
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switch (type) {
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case TessellationType::Isoline:
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return "Isoline";
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case TessellationType::Triangle:
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return "Triangle";
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case TessellationType::Quad:
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return "Quad";
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default:
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return "Unknown";
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}
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}
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enum class TessellationPartitioning : u32 {
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Integer = 0,
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Pow2 = 1,
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FracOdd = 2,
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FracEven = 3,
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};
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constexpr std::string_view NameOf(TessellationPartitioning partitioning) {
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switch (partitioning) {
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case TessellationPartitioning::Integer:
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return "Integer";
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case TessellationPartitioning::Pow2:
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return "Pow2";
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case TessellationPartitioning::FracOdd:
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return "FracOdd";
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case TessellationPartitioning::FracEven:
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return "FracEven";
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default:
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return "Unknown";
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}
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}
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enum class TessellationTopology : u32 {
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Point = 0,
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Line = 1,
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TriangleCw = 2,
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TriangleCcw = 3,
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};
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constexpr std::string_view NameOf(TessellationTopology topology) {
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switch (topology) {
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case TessellationTopology::Point:
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return "Point";
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case TessellationTopology::Line:
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return "Line";
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case TessellationTopology::TriangleCw:
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return "TriangleCw";
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case TessellationTopology::TriangleCcw:
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return "TriangleCcw";
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default:
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return "Unknown";
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}
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}
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// See `VGT_PRIMITIVE_TYPE` description in [Radeon Sea Islands 3D/Compute Register Reference Guide]
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enum class PrimitiveType : u32 {
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None = 0,
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@@ -118,3 +183,33 @@ enum class NumberFormat : u32 {
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};
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} // namespace AmdGpu
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template <>
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struct fmt::formatter<AmdGpu::TessellationType> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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auto format(AmdGpu::TessellationType type, format_context& ctx) const {
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return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(type));
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}
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};
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template <>
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struct fmt::formatter<AmdGpu::TessellationPartitioning> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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auto format(AmdGpu::TessellationPartitioning type, format_context& ctx) const {
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return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(type));
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}
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};
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template <>
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struct fmt::formatter<AmdGpu::TessellationTopology> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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auto format(AmdGpu::TessellationTopology type, format_context& ctx) const {
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return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(type));
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}
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};
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