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vk_rasterizer: Clear depth buffer when DB_RENDER_CONTROL says so
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23f11a3fda
commit
421b52c659
@ -431,7 +431,7 @@ struct Liverpool {
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BitField<28, 4, u32> output7_mask;
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BitField<28, 4, u32> output7_mask;
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[[nodiscard]] u8 GetMask(int buf_id) const {
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[[nodiscard]] u8 GetMask(int buf_id) const {
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return (raw >> (buf_id * 4)) & 0xffu;
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return (raw >> (buf_id * 4)) & 0xfu;
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}
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}
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};
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};
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@ -732,6 +732,20 @@ struct Liverpool {
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float back_offset;
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float back_offset;
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};
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};
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struct Address {
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u32 address;
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VAddr GetAddress() const {
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return u64(address) << 8;
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}
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};
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union DepthRenderControl {
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u32 raw;
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BitField<0, 1, u32> depth_clear_enable;
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BitField<1, 1, u32> stencil_clear_enable;
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};
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union Regs {
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union Regs {
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struct {
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struct {
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INSERT_PADDING_WORDS(0x2C08);
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INSERT_PADDING_WORDS(0x2C08);
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@ -740,11 +754,15 @@ struct Liverpool {
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ShaderProgram vs_program;
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ShaderProgram vs_program;
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INSERT_PADDING_WORDS(0x2E00 - 0x2C4C - 16);
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INSERT_PADDING_WORDS(0x2E00 - 0x2C4C - 16);
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ComputeProgram cs_program;
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ComputeProgram cs_program;
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INSERT_PADDING_WORDS(0xA008 - 0x2E00 - 80);
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INSERT_PADDING_WORDS(0xA008 - 0x2E00 - 80 - 3 - 5);
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DepthRenderControl depth_render_control;
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INSERT_PADDING_WORDS(4);
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Address depth_htile_data_base;
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INSERT_PADDING_WORDS(2);
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float depth_bounds_min;
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float depth_bounds_min;
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float depth_bounds_max;
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float depth_bounds_max;
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u32 stencil_clear;
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u32 stencil_clear;
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u32 depth_clear;
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float depth_clear;
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Scissor screen_scissor;
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Scissor screen_scissor;
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INSERT_PADDING_WORDS(0xA010 - 0xA00C - 2);
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INSERT_PADDING_WORDS(0xA010 - 0xA00C - 2);
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DepthBuffer depth_buffer;
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DepthBuffer depth_buffer;
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@ -925,6 +943,8 @@ static_assert(GFX6_3D_REG_INDEX(cs_program) == 0x2E00);
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static_assert(GFX6_3D_REG_INDEX(cs_program.dim_z) == 0x2E03);
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static_assert(GFX6_3D_REG_INDEX(cs_program.dim_z) == 0x2E03);
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static_assert(GFX6_3D_REG_INDEX(cs_program.address_lo) == 0x2E0C);
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static_assert(GFX6_3D_REG_INDEX(cs_program.address_lo) == 0x2E0C);
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static_assert(GFX6_3D_REG_INDEX(cs_program.user_data) == 0x2E40);
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static_assert(GFX6_3D_REG_INDEX(cs_program.user_data) == 0x2E40);
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static_assert(GFX6_3D_REG_INDEX(depth_render_control) == 0xA000);
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static_assert(GFX6_3D_REG_INDEX(depth_htile_data_base) == 0xA005);
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static_assert(GFX6_3D_REG_INDEX(screen_scissor) == 0xA00C);
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static_assert(GFX6_3D_REG_INDEX(screen_scissor) == 0xA00C);
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static_assert(GFX6_3D_REG_INDEX(depth_buffer.depth_slice) == 0xA017);
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static_assert(GFX6_3D_REG_INDEX(depth_buffer.depth_slice) == 0xA017);
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static_assert(GFX6_3D_REG_INDEX(color_target_mask) == 0xA08E);
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static_assert(GFX6_3D_REG_INDEX(color_target_mask) == 0xA08E);
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@ -942,6 +962,7 @@ static_assert(GFX6_3D_REG_INDEX(color_export_format) == 0xA1C5);
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static_assert(GFX6_3D_REG_INDEX(blend_control) == 0xA1E0);
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static_assert(GFX6_3D_REG_INDEX(blend_control) == 0xA1E0);
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static_assert(GFX6_3D_REG_INDEX(index_base_address) == 0xA1F9);
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static_assert(GFX6_3D_REG_INDEX(index_base_address) == 0xA1F9);
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static_assert(GFX6_3D_REG_INDEX(draw_initiator) == 0xA1FC);
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static_assert(GFX6_3D_REG_INDEX(draw_initiator) == 0xA1FC);
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static_assert(GFX6_3D_REG_INDEX(depth_control) == 0xA200);
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static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
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static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
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static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
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static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
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static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
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static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
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@ -334,6 +334,19 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
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if (data_format == AmdGpu::DataFormat::Format32 && num_format == AmdGpu::NumberFormat::Float) {
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if (data_format == AmdGpu::DataFormat::Format32 && num_format == AmdGpu::NumberFormat::Float) {
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return vk::Format::eR32Sfloat;
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return vk::Format::eR32Sfloat;
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}
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}
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if (data_format == AmdGpu::DataFormat::Format16_16_16_16 &&
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num_format == AmdGpu::NumberFormat::Float) {
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return vk::Format::eR16G16B16A16Sfloat;
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}
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if (data_format == AmdGpu::DataFormat::Format32 && num_format == AmdGpu::NumberFormat::Uint) {
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return vk::Format::eR32Uint;
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}
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if (data_format == AmdGpu::DataFormat::Format32 && num_format == AmdGpu::NumberFormat::Sint) {
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return vk::Format::eR32Sint;
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}
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if (data_format == AmdGpu::DataFormat::Format8_8 && num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eR8G8Unorm;
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}
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UNREACHABLE_MSG("Unknown data_format={} and num_format={}", u32(data_format), u32(num_format));
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UNREACHABLE_MSG("Unknown data_format={} and num_format={}", u32(data_format), u32(num_format));
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}
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}
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@ -60,13 +60,16 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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});
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});
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}
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}
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if (regs.depth_control.depth_enable && regs.depth_buffer.Address() != 0) {
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if (regs.depth_control.depth_enable && regs.depth_buffer.Address() != 0) {
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const bool is_clear = regs.depth_render_control.depth_clear_enable;
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const auto& image_view =
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const auto& image_view =
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texture_cache.DepthTarget(regs.depth_buffer, liverpool->last_db_extent);
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texture_cache.DepthTarget(regs.depth_buffer, liverpool->last_db_extent);
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depth_attachment = {
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depth_attachment = {
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.imageView = *image_view.image_view,
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eGeneral,
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.imageLayout = vk::ImageLayout::eGeneral,
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.loadOp = vk::AttachmentLoadOp::eLoad,
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.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.storeOp = is_clear ? vk::AttachmentStoreOp::eNone : vk::AttachmentStoreOp::eStore,
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
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.stencil = regs.stencil_clear}},
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};
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};
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num_depth_attachments++;
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num_depth_attachments++;
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}
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}
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