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https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-03 16:02:26 +00:00
fix packing
pack is for floats, we have uints here
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parent
12af52348e
commit
43892c8679
@ -233,7 +233,7 @@ private:
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[[nodiscard]] T GetSrc64(const InstOperand& operand);
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[[nodiscard]] T GetSrc64(const InstOperand& operand);
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void SetDst(const InstOperand& operand, const IR::U32F32& value);
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void SetDst(const InstOperand& operand, const IR::U32F32& value);
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void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
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void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
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IR::U16 Convert_F32_to_U16_Normalized(const IR::F32& src);
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IR::U32 Convert_F32_to_U16_Normalized(const IR::F32& src);
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void LogMissingOpcode(const GcnInst& inst);
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void LogMissingOpcode(const GcnInst& inst);
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private:
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private:
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@ -344,25 +344,26 @@ void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_f32));
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ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_f32));
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}
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}
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IR::U16 Translator::Convert_F32_to_U16_Normalized(const IR::F32& src) {
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IR::U32 Translator::Convert_F32_to_U16_Normalized(const IR::F32& src) {
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const IR::F32 as_float = ir.FPMul(src, ir.Imm32((f32)std::numeric_limits<u16>::max()));
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const IR::F32 clamped = ir.FPClamp(src, ir.Imm32(0.0f), ir.Imm32(1.0f));
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const IR::F32 as_float = ir.FPMul(clamped, ir.Imm32((f32)std::numeric_limits<u16>::max()));
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const IR::U32 as_unsigned = ir.ConvertFToU(32, as_float);
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const IR::U32 as_unsigned = ir.ConvertFToU(32, as_float);
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return ir.UConvert(16, as_unsigned);
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return as_unsigned;
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}
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}
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void Translator::V_CVT_PKNORM_U16_F32(const GcnInst& inst) {
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void Translator::V_CVT_PKNORM_U16_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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const IR::F32 src0 = GetSrc<IR::F32>(inst.src[0]);
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const IR::U32 src0 = Convert_F32_to_U16_Normalized(GetSrc<IR::F32>(inst.src[0]));
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const IR::F32 src1 = GetSrc<IR::F32>(inst.src[1]);
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const IR::U32 src1 = Convert_F32_to_U16_Normalized(GetSrc<IR::F32>(inst.src[1]));
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const IR::Value vec_u16 =
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ir.SetVectorReg(
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ir.CompositeConstruct(
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dst_reg,
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Convert_F32_to_U16_Normalized(src0),
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ir.BitwiseOr(
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Convert_F32_to_U16_Normalized(src1)
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src0,
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);
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ir.ShiftLeftLogical(src1, ir.Imm32(16))
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)
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ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_u16));
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);
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}
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}
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void Translator::V_CVT_F32_F16(const GcnInst& inst) {
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void Translator::V_CVT_F32_F16(const GcnInst& inst) {
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