diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
index 2946edab3..c3d937fe7 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
@@ -238,7 +238,7 @@ Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod
         }
         texel = ctx.OpImageRead(color_type, image, coords, operands.mask, operands.operands);
     }
-    return !texture.is_integer ? ctx.OpBitcast(ctx.U32[4], texel) : texel;
+    return texture.is_integer ? ctx.OpBitcast(ctx.F32[4], texel) : texel;
 }
 
 void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod, Id ms,
@@ -253,8 +253,8 @@ void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id
     } else if (Sirit::ValidId(lod)) {
         LOG_WARNING(Render, "Image write with LOD not supported by driver");
     }
-    ctx.OpImageWrite(image, coords, ctx.OpBitcast(color_type, color), operands.mask,
-                     operands.operands);
+    const Id texel = texture.is_integer ? ctx.OpBitcast(color_type, color) : color;
+    ctx.OpImageWrite(image, coords, texel, operands.mask, operands.operands);
 }
 
 } // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/frontend/translate/vector_memory.cpp b/src/shader_recompiler/frontend/translate/vector_memory.cpp
index 48cb79610..461fbf348 100644
--- a/src/shader_recompiler/frontend/translate/vector_memory.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_memory.cpp
@@ -328,7 +328,7 @@ void Translator::BUFFER_STORE_FORMAT(u32 num_dwords, const GcnInst& inst) {
 
     const IR::VectorReg src_reg{inst.src[1].code};
 
-    std::array<IR::Value, 4> comps{};
+    std::array<IR::F32, 4> comps{};
     for (u32 i = 0; i < num_dwords; i++) {
         comps[i] = ir.GetVectorReg<IR::F32>(src_reg + i);
     }
@@ -426,7 +426,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
         if (((mimg.dmask >> i) & 1) == 0) {
             continue;
         }
-        IR::U32 value = IR::U32{ir.CompositeExtract(texel, i)};
+        IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
         ir.SetVectorReg(dest_reg++, value);
     }
 }
diff --git a/src/shader_recompiler/ir/opcodes.inc b/src/shader_recompiler/ir/opcodes.inc
index 7f3c52642..806fe6cf7 100644
--- a/src/shader_recompiler/ir/opcodes.inc
+++ b/src/shader_recompiler/ir/opcodes.inc
@@ -97,7 +97,7 @@ OPCODE(StoreBufferU32,                                      Void,           Opaq
 OPCODE(StoreBufferU32x2,                                    Void,           Opaque,         Opaque,         U32x2,                                          )
 OPCODE(StoreBufferU32x3,                                    Void,           Opaque,         Opaque,         U32x3,                                          )
 OPCODE(StoreBufferU32x4,                                    Void,           Opaque,         Opaque,         U32x4,                                          )
-OPCODE(StoreBufferFormatF32,                                Void,           Opaque,         Opaque,         U32x4,                                          )
+OPCODE(StoreBufferFormatF32,                                Void,           Opaque,         Opaque,         F32x4,                                          )
 
 // Buffer atomic operations
 OPCODE(BufferAtomicIAdd32,                                  U32,            Opaque,         Opaque,         U32                                             )
@@ -353,8 +353,8 @@ OPCODE(ImageGatherDref,                                     F32x4,          Opaq
 OPCODE(ImageQueryDimensions,                                U32x4,          Opaque,         U32,            U1,                                             )
 OPCODE(ImageQueryLod,                                       F32x4,          Opaque,         Opaque,                                                         )
 OPCODE(ImageGradient,                                       F32x4,          Opaque,         Opaque,         Opaque,         Opaque,         Opaque,         F32,         )
-OPCODE(ImageRead,                                           U32x4,          Opaque,         Opaque,         U32,            U32,                            )
-OPCODE(ImageWrite,                                          Void,           Opaque,         Opaque,         U32,            U32,            U32x4,          )
+OPCODE(ImageRead,                                           F32x4,          Opaque,         Opaque,         U32,            U32,                            )
+OPCODE(ImageWrite,                                          Void,           Opaque,         Opaque,         U32,            U32,            F32x4,          )
 
 // Image atomic operations
 OPCODE(ImageAtomicIAdd32,                                   U32,            Opaque,         Opaque,         U32,                                            )
diff --git a/src/shader_recompiler/ir/reinterpret.h b/src/shader_recompiler/ir/reinterpret.h
index 388e69187..73d587a56 100644
--- a/src/shader_recompiler/ir/reinterpret.h
+++ b/src/shader_recompiler/ir/reinterpret.h
@@ -12,8 +12,8 @@ namespace Shader::IR {
 inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::CompMapping& swizzle) {
     // Constants are indexed as 0 and 1, and components are 4-7. Thus we can apply a swizzle
     // using two vectors and a shuffle, using one vector of constants and one of the components.
-    const auto zero = vector.Type() == Type::U32x4 ? Value{ir.Imm32(0u)} : Value{ir.Imm32(0.f)};
-    const auto one = vector.Type() == Type::U32x4 ? Value{ir.Imm32(1u)} : Value{ir.Imm32(1.f)};
+    const auto zero = ir.Imm32(0.f);
+    const auto one = ir.Imm32(1.f);
     const auto constants_vec = ir.CompositeConstruct(zero, one, zero, zero);
     const auto swizzled =
         ir.CompositeShuffle(constants_vec, vector, size_t(swizzle.r), size_t(swizzle.g),