mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
shader_recompiler: Move 10/11-bit float conversion to functions and address some comments.
This commit is contained in:
squidbus
parent
504037cdc6
commit
4f8a6ea81a
@ -155,127 +155,33 @@ Id EmitUnpackSint4x8(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.F32[4], unpacked);
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}
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Id Float32ToUfloatM5(EmitContext& ctx, Id value, u32 mantissa_bits) {
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const auto raw_value{ctx.OpBitcast(ctx.U32[1], value)};
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const auto raw_exponent{
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ctx.OpBitFieldUExtract(ctx.U32[1], raw_value, ctx.ConstU32(23U), ctx.ConstU32(8U))};
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const auto sign{
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ctx.OpBitFieldUExtract(ctx.U32[1], raw_value, ctx.ConstU32(31U), ctx.ConstU32(1U))};
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const auto exponent{
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ctx.OpFSub(ctx.F32[1], ctx.OpConvertUToF(ctx.F32[1], raw_exponent), ctx.ConstF32(127.f))};
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const auto is_zero{ctx.OpLogicalOr(ctx.U1[1],
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ctx.OpIEqual(ctx.U1[1], raw_value, ctx.ConstU32(0U)),
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ctx.OpIEqual(ctx.U1[1], sign, ctx.ConstU32(1U)))};
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const auto is_nan{ctx.OpIsNan(ctx.U1[1], value)};
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const auto is_inf{ctx.OpIsInf(ctx.U1[1], value)};
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const auto is_denorm{ctx.OpFOrdLessThanEqual(ctx.U1[1], exponent, ctx.ConstF32(-15.f))};
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const auto denorm_mantissa{ctx.OpConvertFToU(
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ctx.U32[1],
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ctx.OpRoundEven(ctx.F32[1],
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ctx.OpFMul(ctx.F32[1], value,
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ctx.ConstF32(static_cast<float>(1 << (mantissa_bits + 14))))))};
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const auto denorm_overflow{ctx.OpINotEqual(
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ctx.U1[1],
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ctx.OpShiftRightLogical(ctx.U32[1], denorm_mantissa, ctx.ConstU32(mantissa_bits)),
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ctx.ConstU32(0U))};
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const auto denorm{ctx.OpSelect(ctx.U32[1], denorm_overflow, ctx.ConstU32(1U << mantissa_bits),
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denorm_mantissa)};
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const auto norm_mantissa{ctx.OpConvertFToU(
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ctx.U32[1],
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ctx.OpRoundEven(
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ctx.F32[1],
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ctx.OpFMul(
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ctx.F32[1], value,
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ctx.OpExp2(ctx.F32[1],
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ctx.OpFSub(ctx.F32[1], ctx.ConstF32(static_cast<float>(mantissa_bits)),
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exponent)))))};
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const auto norm_overflow{
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ctx.OpUGreaterThanEqual(ctx.U1[1], norm_mantissa, ctx.ConstU32(2U << mantissa_bits))};
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const auto norm_final_mantissa{ctx.OpBitwiseAnd(
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ctx.U32[1],
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ctx.OpSelect(ctx.U32[1], norm_overflow,
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ctx.OpShiftRightLogical(ctx.U32[1], norm_mantissa, ctx.ConstU32(1U)),
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norm_mantissa),
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ctx.ConstU32((1U << mantissa_bits) - 1))};
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const auto norm_final_exponent{ctx.OpConvertFToU(
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ctx.U32[1],
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ctx.OpFAdd(ctx.F32[1],
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ctx.OpSelect(ctx.F32[1], norm_overflow,
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ctx.OpFAdd(ctx.F32[1], exponent, ctx.ConstF32(1.f)), exponent),
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ctx.ConstF32(15.f)))};
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const auto norm{ctx.OpBitFieldInsert(ctx.U32[1], norm_final_mantissa, norm_final_exponent,
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ctx.ConstU32(mantissa_bits), ctx.ConstU32(5U))};
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return ctx.OpSelect(
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ctx.U32[1], is_zero, ctx.ConstU32(0U),
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ctx.OpSelect(ctx.U32[1], is_nan, ctx.ConstU32(31u << mantissa_bits | 1U),
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ctx.OpSelect(ctx.U32[1], is_inf, ctx.ConstU32(31U << mantissa_bits),
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ctx.OpSelect(ctx.U32[1], is_denorm, denorm, norm))));
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}
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Id EmitPackUfloat10_11_11(EmitContext& ctx, Id value) {
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// No SPIR-V instruction for this, do it manually.
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const auto x{ctx.OpCompositeExtract(ctx.F32[1], value, 0)};
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const auto y{ctx.OpCompositeExtract(ctx.F32[1], value, 1)};
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const auto z{ctx.OpCompositeExtract(ctx.F32[1], value, 2)};
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auto result = Float32ToUfloatM5(ctx, x, 6U);
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result = ctx.OpBitFieldInsert(ctx.U32[1], result, Float32ToUfloatM5(ctx, y, 6U),
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ctx.ConstU32(11U), ctx.ConstU32(11U));
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result = ctx.OpBitFieldInsert(ctx.U32[1], result, Float32ToUfloatM5(ctx, z, 5U),
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ctx.ConstU32(22U), ctx.ConstU32(10U));
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const auto cvt_x{ctx.OpFunctionCall(ctx.U32[1], ctx.f32_to_uf11, x)};
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const auto cvt_y{ctx.OpFunctionCall(ctx.U32[1], ctx.f32_to_uf11, y)};
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const auto cvt_z{ctx.OpFunctionCall(ctx.U32[1], ctx.f32_to_uf10, z)};
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auto result = cvt_x;
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result = ctx.OpBitFieldInsert(ctx.U32[1], result, cvt_y, ctx.ConstU32(11U), ctx.ConstU32(11U));
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result = ctx.OpBitFieldInsert(ctx.U32[1], result, cvt_z, ctx.ConstU32(22U), ctx.ConstU32(10U));
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return result;
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}
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Id UfloatM5ToFloat32(EmitContext& ctx, Id value, u32 mantissa_bits) {
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const auto raw_mantissa{
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ctx.OpBitFieldUExtract(ctx.U32[1], value, ctx.ConstU32(0U), ctx.ConstU32(mantissa_bits))};
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const auto raw_exponent{
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ctx.OpBitFieldUExtract(ctx.U32[1], value, ctx.ConstU32(mantissa_bits), ctx.ConstU32(5U))};
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const auto is_exp_max{ctx.OpIEqual(ctx.U1[1], raw_exponent, ctx.ConstU32(31u))};
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const auto is_exp_min{ctx.OpIEqual(ctx.U1[1], raw_exponent, ctx.ConstU32(0u))};
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const auto is_zero{ctx.OpIEqual(ctx.U1[1], value, ctx.ConstU32(0u))};
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const auto is_nan{ctx.OpLogicalAnd(ctx.U1[1], is_exp_max,
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ctx.OpINotEqual(ctx.U1[1], raw_mantissa, ctx.ConstU32(0u)))};
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const auto is_inf{ctx.OpLogicalAnd(ctx.U1[1], is_exp_max,
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ctx.OpIEqual(ctx.U1[1], raw_mantissa, ctx.ConstU32(0u)))};
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const auto is_denorm{ctx.OpLogicalAnd(
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ctx.U1[1], is_exp_min, ctx.OpINotEqual(ctx.U1[1], raw_mantissa, ctx.ConstU32(0u)))};
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const auto mantissa{ctx.OpConvertUToF(ctx.F32[1], raw_mantissa)};
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const auto exponent{
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ctx.OpFSub(ctx.F32[1], ctx.OpConvertUToF(ctx.F32[1], raw_exponent), ctx.ConstF32(15.f))};
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const auto denorm{ctx.OpFMul(ctx.F32[1], mantissa, ctx.ConstF32(1.f / (1 << 20)))};
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const auto norm{ctx.OpFMul(
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ctx.F32[1],
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ctx.OpFAdd(ctx.F32[1],
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ctx.OpFMul(ctx.F32[1], mantissa,
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ctx.ConstF32(1.f / static_cast<float>(1 << mantissa_bits))),
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ctx.ConstF32(1.f)),
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ctx.OpExp2(ctx.F32[1], exponent))};
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return ctx.OpSelect(
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ctx.F32[1], is_zero, ctx.ConstF32(0.f),
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ctx.OpSelect(ctx.F32[1], is_nan, ctx.ConstF32(NAN),
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ctx.OpSelect(ctx.F32[1], is_inf, ctx.ConstF32(INFINITY),
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ctx.OpSelect(ctx.F32[1], is_denorm, denorm, norm))));
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}
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Id EmitUnpackUfloat10_11_11(EmitContext& ctx, Id value) {
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// No SPIR-V instruction for this, do it manually.
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const auto x{ctx.OpBitFieldUExtract(ctx.U32[1], value, ctx.ConstU32(0U), ctx.ConstU32(11U))};
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const auto y{ctx.OpBitFieldUExtract(ctx.U32[1], value, ctx.ConstU32(11U), ctx.ConstU32(11U))};
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const auto z{ctx.OpBitFieldUExtract(ctx.U32[1], value, ctx.ConstU32(22U), ctx.ConstU32(10U))};
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return ctx.OpCompositeConstruct(ctx.F32[3], UfloatM5ToFloat32(ctx, x, 6U),
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UfloatM5ToFloat32(ctx, y, 6U), UfloatM5ToFloat32(ctx, z, 5U));
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const auto cvt_x{ctx.OpFunctionCall(ctx.F32[1], ctx.uf11_to_f32, x)};
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const auto cvt_y{ctx.OpFunctionCall(ctx.F32[1], ctx.uf11_to_f32, y)};
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const auto cvt_z{ctx.OpFunctionCall(ctx.F32[1], ctx.uf10_to_f32, z)};
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return ctx.OpCompositeConstruct(ctx.F32[3], cvt_x, cvt_y, cvt_z);
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}
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Id EmitPackUnorm2_10_10_10(EmitContext& ctx, Id value) {
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@ -75,6 +75,7 @@ EmitContext::EmitContext(const Profile& profile_, const RuntimeInfo& runtime_inf
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DefineSharedMemory();
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DefineBuffers();
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DefineImagesAndSamplers();
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DefineFunctions();
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}
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EmitContext::~EmitContext() = default;
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@ -853,4 +854,117 @@ void EmitContext::DefineSharedMemory() {
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}
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}
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Id EmitContext::DefineFloat32ToUfloatM5(u32 mantissa_bits, const std::string_view name) {
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// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/util/format_r11g11b10f.h
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const auto func_type{TypeFunction(U32[1], F32[1])};
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const auto func{OpFunction(U32[1], spv::FunctionControlMask::MaskNone, func_type)};
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const auto value{OpFunctionParameter(F32[1])};
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Name(func, name);
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AddLabel();
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const auto raw_value{OpBitcast(U32[1], value)};
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const auto exponent{
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OpBitcast(S32[1], OpBitFieldSExtract(U32[1], raw_value, ConstU32(23U), ConstU32(8U)))};
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const auto sign{OpBitFieldUExtract(U32[1], raw_value, ConstU32(31U), ConstU32(1U))};
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const auto is_zero{OpLogicalOr(U1[1], OpIEqual(U1[1], raw_value, ConstU32(0U)),
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OpIEqual(U1[1], sign, ConstU32(1U)))};
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const auto is_nan{OpIsNan(U1[1], value)};
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const auto is_inf{OpIsInf(U1[1], value)};
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const auto is_denorm{OpSLessThanEqual(U1[1], exponent, ConstS32(-15))};
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const auto denorm_mantissa{OpConvertFToU(
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U32[1],
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OpRoundEven(F32[1], OpFMul(F32[1], value,
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ConstF32(static_cast<float>(1 << (mantissa_bits + 14))))))};
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const auto denorm_overflow{
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OpINotEqual(U1[1], OpShiftRightLogical(U32[1], denorm_mantissa, ConstU32(mantissa_bits)),
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ConstU32(0U))};
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const auto denorm{
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OpSelect(U32[1], denorm_overflow, ConstU32(1U << mantissa_bits), denorm_mantissa)};
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const auto norm_mantissa{OpConvertFToU(
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U32[1],
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OpRoundEven(F32[1],
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OpLdexp(F32[1], value,
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OpISub(S32[1], ConstS32(static_cast<int>(mantissa_bits)), exponent))))};
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const auto norm_overflow{
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OpUGreaterThanEqual(U1[1], norm_mantissa, ConstU32(2U << mantissa_bits))};
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const auto norm_final_mantissa{OpBitwiseAnd(
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U32[1],
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OpSelect(U32[1], norm_overflow, OpShiftRightLogical(U32[1], norm_mantissa, ConstU32(1U)),
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norm_mantissa),
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ConstU32((1U << mantissa_bits) - 1))};
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const auto norm_final_exponent{OpBitcast(
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U32[1],
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OpIAdd(S32[1],
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OpSelect(S32[1], norm_overflow, OpIAdd(S32[1], exponent, ConstS32(1)), exponent),
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ConstS32(15)))};
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const auto norm{OpBitFieldInsert(U32[1], norm_final_mantissa, norm_final_exponent,
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ConstU32(mantissa_bits), ConstU32(5U))};
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const auto result{OpSelect(U32[1], is_zero, ConstU32(0U),
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OpSelect(U32[1], is_nan, ConstU32(31u << mantissa_bits | 1U),
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OpSelect(U32[1], is_inf, ConstU32(31U << mantissa_bits),
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OpSelect(U32[1], is_denorm, denorm, norm))))};
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OpReturnValue(result);
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OpFunctionEnd();
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return func;
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}
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Id EmitContext::DefineUfloatM5ToFloat32(u32 mantissa_bits, const std::string_view name) {
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// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/util/format_r11g11b10f.h
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const auto func_type{TypeFunction(F32[1], U32[1])};
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const auto func{OpFunction(F32[1], spv::FunctionControlMask::MaskNone, func_type)};
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const auto value{OpFunctionParameter(U32[1])};
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Name(func, name);
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AddLabel();
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const auto raw_mantissa{
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OpBitFieldUExtract(U32[1], value, ConstU32(0U), ConstU32(mantissa_bits))};
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const auto mantissa{OpConvertUToF(F32[1], raw_mantissa)};
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const auto exponent{OpBitcast(
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S32[1], OpBitFieldSExtract(U32[1], value, ConstU32(mantissa_bits), ConstU32(5U)))};
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const auto is_exp_neg_one{OpIEqual(U1[1], exponent, ConstS32(-1))};
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const auto is_exp_zero{OpIEqual(U1[1], exponent, ConstS32(0))};
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const auto is_zero{OpIEqual(U1[1], value, ConstU32(0u))};
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const auto is_nan{
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OpLogicalAnd(U1[1], is_exp_neg_one, OpINotEqual(U1[1], raw_mantissa, ConstU32(0u)))};
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const auto is_inf{
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OpLogicalAnd(U1[1], is_exp_neg_one, OpIEqual(U1[1], raw_mantissa, ConstU32(0u)))};
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const auto is_denorm{
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OpLogicalAnd(U1[1], is_exp_zero, OpINotEqual(U1[1], raw_mantissa, ConstU32(0u)))};
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const auto denorm{OpFMul(F32[1], mantissa, ConstF32(1.f / (1 << 20)))};
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const auto norm{OpLdexp(
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F32[1],
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OpFAdd(F32[1],
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OpFMul(F32[1], mantissa, ConstF32(1.f / static_cast<float>(1 << mantissa_bits))),
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ConstF32(1.f)),
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exponent)};
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const auto result{OpSelect(F32[1], is_zero, ConstF32(0.f),
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OpSelect(F32[1], is_nan, ConstF32(NAN),
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OpSelect(F32[1], is_inf, ConstF32(INFINITY),
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OpSelect(F32[1], is_denorm, denorm, norm))))};
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OpReturnValue(result);
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OpFunctionEnd();
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return func;
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}
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void EmitContext::DefineFunctions() {
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if (info.uses_pack_10_11_11) {
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f32_to_uf11 = DefineFloat32ToUfloatM5(6, "f32_to_uf11");
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f32_to_uf10 = DefineFloat32ToUfloatM5(5, "f32_to_uf10");
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}
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if (info.uses_unpack_10_11_11) {
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uf11_to_f32 = DefineUfloatM5ToFloat32(6, "uf11_to_f32");
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uf10_to_f32 = DefineUfloatM5ToFloat32(5, "uf10_to_f32");
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}
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}
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} // namespace Shader::Backend::SPIRV
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@ -260,6 +260,11 @@ public:
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std::array<SpirvAttribute, IR::NumParams> output_params{};
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std::array<SpirvAttribute, IR::NumRenderTargets> frag_outputs{};
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Id uf11_to_f32{};
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Id f32_to_uf11{};
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Id uf10_to_f32{};
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Id f32_to_uf10{};
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private:
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void DefineArithmeticTypes();
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void DefineInterfaces();
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@ -269,9 +274,13 @@ private:
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void DefineBuffers();
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void DefineImagesAndSamplers();
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void DefineSharedMemory();
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void DefineFunctions();
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SpirvAttribute GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id, u32 num_components,
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bool output);
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Id DefineFloat32ToUfloatM5(u32 mantissa_bits, std::string_view name);
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Id DefineUfloatM5ToFloat32(u32 mantissa_bits, std::string_view name);
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};
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} // namespace Shader::Backend::SPIRV
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@ -189,6 +189,8 @@ struct Info {
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bool uses_shared{};
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bool uses_fp16{};
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bool uses_fp64{};
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bool uses_pack_10_11_11{};
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bool uses_unpack_10_11_11{};
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bool stores_tess_level_outer{};
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bool stores_tess_level_inner{};
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bool translation_failed{}; // indicates that shader has unsupported instructions
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@ -76,6 +76,12 @@ void Visit(Info& info, const IR::Inst& inst) {
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case IR::Opcode::ReadConst:
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info.has_readconst = true;
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break;
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case IR::Opcode::PackUfloat10_11_11:
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info.uses_pack_10_11_11 = true;
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break;
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case IR::Opcode::UnpackUfloat10_11_11:
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info.uses_unpack_10_11_11 = true;
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break;
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default:
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break;
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}
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@ -435,28 +435,6 @@ bool Rasterizer::BindResources(const Pipeline* pipeline) {
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if (pipeline->IsCompute()) {
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const auto& info = pipeline->GetStage(Shader::LogicalStage::Compute);
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// Most of the time when a metadata is updated with a shader it gets cleared. It means
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// we can skip the whole dispatch and update the tracked state instead. Also, it is not
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// intended to be consumed and in such rare cases (e.g. HTile introspection, CRAA) we
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// will need its full emulation anyways. For cases of metadata read a warning will be
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// logged.
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const auto IsMetaUpdate = [&](const auto& desc) {
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const auto sharp = desc.GetSharp(info);
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const VAddr address = sharp.base_address;
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if (desc.is_written) {
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// Assume all slices were updates
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if (texture_cache.ClearMeta(address)) {
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LOG_TRACE(Render_Vulkan, "Metadata update skipped");
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return true;
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}
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} else {
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if (texture_cache.IsMeta(address)) {
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LOG_WARNING(Render_Vulkan, "Unexpected metadata read by a CS shader (buffer)");
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}
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}
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return false;
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};
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||||
// Assume if a shader reads and writes metas at the same time, it is a copy shader.
|
||||
bool meta_read = false;
|
||||
for (const auto& desc : info.buffers) {
|
||||
@ -469,10 +447,26 @@ bool Rasterizer::BindResources(const Pipeline* pipeline) {
|
||||
}
|
||||
}
|
||||
|
||||
// Most of the time when a metadata is updated with a shader it gets cleared. It means
|
||||
// we can skip the whole dispatch and update the tracked state instead. Also, it is not
|
||||
// intended to be consumed and in such rare cases (e.g. HTile introspection, CRAA) we
|
||||
// will need its full emulation anyways. For cases of metadata read a warning will be
|
||||
// logged.
|
||||
if (!meta_read) {
|
||||
for (const auto& desc : info.buffers) {
|
||||
if (IsMetaUpdate(desc)) {
|
||||
return false;
|
||||
const auto sharp = desc.GetSharp(info);
|
||||
const VAddr address = sharp.base_address;
|
||||
if (desc.is_written) {
|
||||
// Assume all slices were updates
|
||||
if (texture_cache.ClearMeta(address)) {
|
||||
LOG_TRACE(Render_Vulkan, "Metadata update skipped");
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
if (texture_cache.IsMeta(address)) {
|
||||
LOG_WARNING(Render_Vulkan,
|
||||
"Unexpected metadata read by a CS shader (buffer)");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user