From 66ac528ae40f3d930d3a4b34b6ae9cc5254caced Mon Sep 17 00:00:00 2001 From: DanielSvoboda Date: Sun, 28 Jul 2024 22:12:46 -0300 Subject: [PATCH] Update translate.cpp --- .../frontend/translate/translate.cpp | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/translate.cpp b/src/shader_recompiler/frontend/translate/translate.cpp index bebef8575..d525490f9 100644 --- a/src/shader_recompiler/frontend/translate/translate.cpp +++ b/src/shader_recompiler/frontend/translate/translate.cpp @@ -138,7 +138,11 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) { value = ir.Imm32(-0.5f); break; case OperandField::ConstFloatNeg_1_0: - value = ir.Imm32(-1.0f); + if (force_flt) { + value = ir.Imm32(-1.0f); + } else { + value = ir.Imm32(-1); + } break; case OperandField::ConstFloatNeg_2_0: value = ir.Imm32(-2.0f); @@ -475,6 +479,12 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::S_MUL_I32: translator.S_MUL_I32(inst); break; + case Opcode::S_MIN_U32: + translator.S_MIN_U32(inst); + break; + case Opcode::S_MAX_U32: + translator.S_MAX_U32(inst); + break; case Opcode::V_MAD_F32: translator.V_MAD_F32(inst); break; @@ -700,6 +710,9 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::V_CMP_LT_F32: translator.V_CMP_F32(ConditionOp::LT, false, inst); break; + case Opcode::V_CMP_U_F32: + translator.V_CMP_F32(ConditionOp::U, false, inst); + break; case Opcode::V_CMP_EQ_F32: translator.V_CMP_F32(ConditionOp::EQ, false, inst); break; @@ -745,6 +758,9 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::S_CMP_GT_I32: translator.S_CMP(ConditionOp::GT, true, inst); break; + case Opcode::S_CMP_GT_U32: + translator.S_CMP(ConditionOp::GT, false, inst); + break; case Opcode::S_CMP_GE_I32: translator.S_CMP(ConditionOp::GE, true, inst); break; @@ -855,6 +871,9 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::V_MIN3_F32: translator.V_MIN3_F32(inst); break; + case Opcode::V_MIN3_I32: + translator.V_MIN3_I32(inst); + break; case Opcode::V_MIN_LEGACY_F32: translator.V_MIN_F32(inst, true); break; @@ -1136,6 +1155,9 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::DS_READ2_B32: translator.DS_READ(32, false, true, inst); break; + case Opcode::DS_READ2_B64: + translator.DS_READ(64, false, false, inst); + break; case Opcode::DS_READ_B64: translator.DS_READ(64, false, false, inst); break; @@ -1160,6 +1182,12 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::S_GETPC_B64: translator.S_GETPC_B64(block_base, inst); break; + case Opcode::V_MBCNT_LO_U32_B32: + translator.V_MBCNT_U32_B32(true, inst); + break; + case Opcode::V_MBCNT_HI_U32_B32: + translator.V_MBCNT_U32_B32(false, inst); + break; case Opcode::S_NOP: case Opcode::S_CBRANCH_EXECZ: case Opcode::S_CBRANCH_SCC0: @@ -1170,6 +1198,9 @@ void Translate(IR::Block* block, u32 block_base, std::span inst_l case Opcode::S_WQM_B64: case Opcode::V_INTERP_P1_F32: case Opcode::S_ENDPGM: + case Opcode::BUFFER_ATOMIC_ADD: + case Opcode::BUFFER_ATOMIC_UMIN: + case Opcode::BUFFER_ATOMIC_UMAX: break; default: const u32 opcode = u32(inst.opcode);