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shader_recompiler: Improve shader exports accuracy (part 1) (#3447)
* video_core: support for RT layer outputs - support for RT layer outputs - refactor for handling of export attributes - move output->attribute mapping to a separate header * export: Rework render target exports - Centralize all code related to MRT exports into a single function to make it easier to follow - Apply swizzle to output RGBA colors instead of the render target channel. This fixes swizzles on formats with < 4 channels For example with render target format R8_UNORM and COMP_SWAP ALT_REV the previous code would output frag_color.a = color.r; instead of frag_color.r = color.a; which would result in incorrect output in some cases * vk_pipeline_cache: Apply swizzle to write masks --------- Co-authored-by: polyproxy <47796739+polybiusproxy@users.noreply.github.com>
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@@ -539,24 +539,26 @@ void EmitContext::DefineInputs() {
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}
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}
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void EmitContext::DefineVertexBlock() {
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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if (info.stores.GetAny(IR::Attribute::ClipDistance)) {
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clip_distances = DefineVariable(TypeArray(F32[1], ConstU32(8U)), spv::BuiltIn::ClipDistance,
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spv::StorageClass::Output);
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}
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if (info.stores.GetAny(IR::Attribute::CullDistance)) {
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cull_distances = DefineVariable(TypeArray(F32[1], ConstU32(8U)), spv::BuiltIn::CullDistance,
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spv::StorageClass::Output);
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}
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if (info.stores.GetAny(IR::Attribute::RenderTargetId)) {
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output_layer = DefineVariable(S32[1], spv::BuiltIn::Layer, spv::StorageClass::Output);
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}
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}
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void EmitContext::DefineOutputs() {
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switch (l_stage) {
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case LogicalStage::Vertex: {
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// No point in defining builtin outputs (i.e. position) unless next stage is fragment?
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// Might cause problems linking with tcs
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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const bool has_extra_pos_stores = info.stores.Get(IR::Attribute::Position1) ||
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info.stores.Get(IR::Attribute::Position2) ||
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info.stores.Get(IR::Attribute::Position3);
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if (has_extra_pos_stores) {
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const Id type{TypeArray(F32[1], ConstU32(8U))};
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clip_distances =
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DefineVariable(type, spv::BuiltIn::ClipDistance, spv::StorageClass::Output);
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cull_distances =
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DefineVariable(type, spv::BuiltIn::CullDistance, spv::StorageClass::Output);
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}
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if (stage == Stage::Local) {
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DefineVertexBlock();
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if (stage == Shader::Stage::Local) {
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const u32 num_attrs = Common::AlignUp(runtime_info.ls_info.ls_stride, 16) >> 4;
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if (num_attrs > 0) {
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const Id type{TypeArray(F32[4], ConstU32(num_attrs))};
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@@ -615,17 +617,7 @@ void EmitContext::DefineOutputs() {
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break;
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}
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case LogicalStage::TessellationEval: {
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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const bool has_extra_pos_stores = info.stores.Get(IR::Attribute::Position1) ||
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info.stores.Get(IR::Attribute::Position2) ||
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info.stores.Get(IR::Attribute::Position3);
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if (has_extra_pos_stores) {
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const Id type{TypeArray(F32[1], ConstU32(8U))};
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clip_distances =
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DefineVariable(type, spv::BuiltIn::ClipDistance, spv::StorageClass::Output);
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cull_distances =
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DefineVariable(type, spv::BuiltIn::CullDistance, spv::StorageClass::Output);
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}
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DefineVertexBlock();
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for (u32 i = 0; i < IR::NumParams; i++) {
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const IR::Attribute param{IR::Attribute::Param0 + i};
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if (!info.stores.GetAny(param)) {
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@@ -665,8 +657,7 @@ void EmitContext::DefineOutputs() {
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break;
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}
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case LogicalStage::Geometry: {
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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DefineVertexBlock();
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for (u32 attr_id = 0; attr_id < info.gs_copy_data.num_attrs; attr_id++) {
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const Id id{DefineOutput(F32[4], attr_id)};
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Name(id, fmt::format("out_attr{}", attr_id));
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