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shader_recompiler: Improve shader exports accuracy (part 1) (#3447)
* video_core: support for RT layer outputs - support for RT layer outputs - refactor for handling of export attributes - move output->attribute mapping to a separate header * export: Rework render target exports - Centralize all code related to MRT exports into a single function to make it easier to follow - Apply swizzle to output RGBA colors instead of the render target channel. This fixes swizzles on formats with < 4 channels For example with render target format R8_UNORM and COMP_SWAP ALT_REV the previous code would output frag_color.a = color.r; instead of frag_color.r = color.a; which would result in incorrect output in some cases * vk_pipeline_cache: Apply swizzle to write masks --------- Co-authored-by: polyproxy <47796739+polybiusproxy@users.noreply.github.com>
This commit is contained in:
TheTurtle
GitHub
@@ -2,134 +2,113 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/position.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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u32 SwizzleMrtComponent(const PsColorBuffer& color_buffer, u32 comp) {
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const auto [r, g, b, a] = color_buffer.swizzle;
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const std::array swizzle_array = {r, g, b, a};
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const auto swizzled_comp_type = static_cast<u32>(swizzle_array[comp]);
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constexpr auto min_comp_type = static_cast<u32>(AmdGpu::CompSwizzle::Red);
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return swizzled_comp_type >= min_comp_type ? swizzled_comp_type - min_comp_type : comp;
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}
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void Translator::ExportMrtValue(IR::Attribute attribute, u32 comp, const IR::F32& value,
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const PsColorBuffer& color_buffer) {
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auto converted = ApplyWriteNumberConversion(ir, value, color_buffer.num_conversion);
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if (color_buffer.needs_unorm_fixup) {
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// FIXME: Fix-up for GPUs where float-to-unorm rounding is off from expected.
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converted = ir.FPSub(converted, ir.Imm32(1.f / 127500.f));
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}
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ir.SetAttribute(attribute, converted, comp);
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}
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void Translator::ExportMrtCompressed(IR::Attribute attribute, u32 idx, const IR::U32& value) {
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u32 color_buffer_idx =
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static_cast<u32>(attribute) - static_cast<u32>(IR::Attribute::RenderTarget0);
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if (runtime_info.fs_info.dual_source_blending && attribute == IR::Attribute::RenderTarget1) {
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color_buffer_idx = 0;
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}
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const auto color_buffer = runtime_info.fs_info.color_buffers[color_buffer_idx];
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AmdGpu::NumberFormat num_format;
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switch (color_buffer.export_format) {
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case AmdGpu::Liverpool::ShaderExportFormat::Zero:
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// No export
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return;
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static AmdGpu::NumberFormat NumberFormatCompressed(
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AmdGpu::Liverpool::ShaderExportFormat export_format) {
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switch (export_format) {
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_FP16:
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num_format = AmdGpu::NumberFormat::Float;
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break;
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return AmdGpu::NumberFormat::Float;
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_UNORM16:
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num_format = AmdGpu::NumberFormat::Unorm;
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break;
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return AmdGpu::NumberFormat::Unorm;
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_SNORM16:
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num_format = AmdGpu::NumberFormat::Snorm;
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break;
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return AmdGpu::NumberFormat::Snorm;
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_UINT16:
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num_format = AmdGpu::NumberFormat::Uint;
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break;
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return AmdGpu::NumberFormat::Uint;
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_SINT16:
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num_format = AmdGpu::NumberFormat::Sint;
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break;
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return AmdGpu::NumberFormat::Sint;
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default:
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UNREACHABLE_MSG("Unimplemented compressed MRT export format {}",
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static_cast<u32>(color_buffer.export_format));
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break;
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static_cast<u32>(export_format));
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}
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const auto unpacked_value = ir.Unpack2x16(num_format, value);
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const IR::F32 r = IR::F32{ir.CompositeExtract(unpacked_value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(unpacked_value, 1)};
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const auto swizzled_r = SwizzleMrtComponent(color_buffer, idx * 2);
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const auto swizzled_g = SwizzleMrtComponent(color_buffer, idx * 2 + 1);
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ExportMrtValue(attribute, swizzled_r, r, color_buffer);
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ExportMrtValue(attribute, swizzled_g, g, color_buffer);
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}
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void Translator::ExportMrtUncompressed(IR::Attribute attribute, u32 comp, const IR::F32& value) {
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u32 color_buffer_idx =
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static_cast<u32>(attribute) - static_cast<u32>(IR::Attribute::RenderTarget0);
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if (runtime_info.fs_info.dual_source_blending && attribute == IR::Attribute::RenderTarget1) {
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color_buffer_idx = 0;
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}
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const auto color_buffer = runtime_info.fs_info.color_buffers[color_buffer_idx];
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const auto swizzled_comp = SwizzleMrtComponent(color_buffer, comp);
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switch (color_buffer.export_format) {
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case AmdGpu::Liverpool::ShaderExportFormat::Zero:
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// No export
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return;
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static u32 MaskFromExportFormat(u8 mask, AmdGpu::Liverpool::ShaderExportFormat export_format) {
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switch (export_format) {
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case AmdGpu::Liverpool::ShaderExportFormat::R_32:
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// Red only
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if (swizzled_comp != 0) {
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return;
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}
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break;
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return mask & 1;
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case AmdGpu::Liverpool::ShaderExportFormat::GR_32:
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// Red and Green only
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if (swizzled_comp != 0 && swizzled_comp != 1) {
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return;
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}
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break;
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return mask & 3;
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case AmdGpu::Liverpool::ShaderExportFormat::AR_32:
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// Red and Alpha only
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if (swizzled_comp != 0 && swizzled_comp != 3) {
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return;
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}
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break;
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return mask & 9;
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case AmdGpu::Liverpool::ShaderExportFormat::ABGR_32:
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// All components
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break;
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return mask;
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default:
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UNREACHABLE_MSG("Unimplemented uncompressed MRT export format {}",
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static_cast<u32>(color_buffer.export_format));
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break;
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static_cast<u32>(export_format));
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}
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ExportMrtValue(attribute, swizzled_comp, value, color_buffer);
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}
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void Translator::ExportCompressed(IR::Attribute attribute, u32 idx, const IR::U32& value) {
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if (IsMrt(attribute)) {
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ExportMrtCompressed(attribute, idx, value);
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return;
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}
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const IR::Value unpacked_value = ir.Unpack2x16(AmdGpu::NumberFormat::Float, value);
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const IR::F32 r = IR::F32{ir.CompositeExtract(unpacked_value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(unpacked_value, 1)};
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ir.SetAttribute(attribute, r, idx * 2);
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ir.SetAttribute(attribute, g, idx * 2 + 1);
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}
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void Translator::ExportRenderTarget(const GcnInst& inst) {
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const auto& exp = inst.control.exp;
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const IR::Attribute mrt{exp.target};
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info.mrt_mask |= 1u << static_cast<u8>(mrt);
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void Translator::ExportUncompressed(IR::Attribute attribute, u32 comp, const IR::F32& value) {
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if (IsMrt(attribute)) {
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ExportMrtUncompressed(attribute, comp, value);
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// Dual source blending uses MRT1 for exporting src1
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u32 color_buffer_idx = static_cast<u32>(mrt) - static_cast<u32>(IR::Attribute::RenderTarget0);
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if (runtime_info.fs_info.dual_source_blending && mrt == IR::Attribute::RenderTarget1) {
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color_buffer_idx = 0;
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}
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const auto color_buffer = runtime_info.fs_info.color_buffers[color_buffer_idx];
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if (color_buffer.export_format == AmdGpu::Liverpool::ShaderExportFormat::Zero || exp.en == 0) {
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// No export
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return;
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}
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ir.SetAttribute(attribute, value, comp);
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std::array<IR::F32, 4> components{};
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if (exp.compr) {
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// Components are float16 packed into a VGPR
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const auto num_format = NumberFormatCompressed(color_buffer.export_format);
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// Export R, G
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if (exp.en & 1) {
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const IR::Value unpacked_value =
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ir.Unpack2x16(num_format, ir.GetVectorReg(IR::VectorReg(inst.src[0].code)));
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components[0] = IR::F32{ir.CompositeExtract(unpacked_value, 0)};
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components[1] = IR::F32{ir.CompositeExtract(unpacked_value, 1)};
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}
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// Export B, A
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if ((exp.en >> 2) & 1) {
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const IR::Value unpacked_value =
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ir.Unpack2x16(num_format, ir.GetVectorReg(IR::VectorReg(inst.src[1].code)));
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components[2] = IR::F32{ir.CompositeExtract(unpacked_value, 0)};
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components[3] = IR::F32{ir.CompositeExtract(unpacked_value, 1)};
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}
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} else {
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// Components are float32 into separate VGPRS
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u32 mask = MaskFromExportFormat(exp.en, color_buffer.export_format);
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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components[i] = ir.GetVectorReg<IR::F32>(IR::VectorReg(inst.src[i].code));
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}
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}
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// Swizzle components and export
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for (u32 i = 0; i < 4; ++i) {
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const u32 comp_swizzle = static_cast<u32>(color_buffer.swizzle.array[i]);
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constexpr u32 min_swizzle = static_cast<u32>(AmdGpu::CompSwizzle::Red);
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const auto swizzled_comp =
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components[comp_swizzle >= min_swizzle ? comp_swizzle - min_swizzle : i];
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if (swizzled_comp.IsEmpty()) {
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continue;
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}
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auto converted = ApplyWriteNumberConversion(ir, swizzled_comp, color_buffer.num_conversion);
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if (color_buffer.needs_unorm_fixup) {
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// FIXME: Fix-up for GPUs where float-to-unorm rounding is off from expected.
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converted = ir.FPSub(converted, ir.Imm32(1.f / 127500.f));
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}
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ir.SetAttribute(mrt, converted, i);
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}
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}
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void Translator::EmitExport(const GcnInst& inst) {
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@@ -139,40 +118,27 @@ void Translator::EmitExport(const GcnInst& inst) {
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const auto& exp = inst.control.exp;
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const IR::Attribute attrib{exp.target};
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if (IR::IsMrt(attrib)) {
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return ExportRenderTarget(inst);
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}
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ASSERT_MSG(!exp.compr, "Compressed exports only supported for render targets");
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if (attrib == IR::Attribute::Depth && exp.en != 0 && exp.en != 1) {
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LOG_WARNING(Render_Vulkan, "Unsupported depth export");
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return;
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}
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const std::array vsrc = {
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IR::VectorReg(inst.src[0].code),
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IR::VectorReg(inst.src[1].code),
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IR::VectorReg(inst.src[2].code),
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IR::VectorReg(inst.src[3].code),
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};
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// Components are float16 packed into a VGPR
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if (exp.compr) {
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// Export R, G
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if (exp.en & 1) {
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ExportCompressed(attrib, 0, ir.GetVectorReg<IR::U32>(vsrc[0]));
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u32 mask = exp.en;
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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// Export B, A
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if ((exp.en >> 2) & 1) {
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ExportCompressed(attrib, 1, ir.GetVectorReg<IR::U32>(vsrc[1]));
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const auto value = ir.GetVectorReg<IR::F32>(IR::VectorReg(inst.src[i].code));
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if (IsPosition(attrib)) {
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IR::ExportPosition(ir, runtime_info.vs_info, attrib, i, value);
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} else {
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ir.SetAttribute(attrib, value, i);
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}
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} else {
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// Components are float32 into separate VGPRS
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u32 mask = exp.en;
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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ExportUncompressed(attrib, i, ir.GetVectorReg<IR::F32>(vsrc[i]));
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}
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}
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if (IR::IsMrt(attrib)) {
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info.mrt_mask |= 1u << u8(attrib);
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}
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}
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@@ -317,13 +317,7 @@ private:
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IR::F32 SelectCubeResult(const IR::F32& x, const IR::F32& y, const IR::F32& z,
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const IR::F32& x_res, const IR::F32& y_res, const IR::F32& z_res);
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void ExportMrtValue(IR::Attribute attribute, u32 comp, const IR::F32& value,
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const PsColorBuffer& color_buffer);
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void ExportMrtCompressed(IR::Attribute attribute, u32 idx, const IR::U32& value);
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void ExportMrtUncompressed(IR::Attribute attribute, u32 comp, const IR::F32& value);
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void ExportCompressed(IR::Attribute attribute, u32 idx, const IR::U32& value);
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void ExportUncompressed(IR::Attribute attribute, u32 comp, const IR::F32& value);
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void ExportRenderTarget(const GcnInst& inst);
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void LogMissingOpcode(const GcnInst& inst);
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IR::VectorReg GetScratchVgpr(u32 offset);
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