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shader_recompiler: Add bit instructions

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This commit is contained in:
IndecisiveTurtle 2024-07-29 19:08:43 +03:00
parent 32fd1991f7
commit 7d494b88a6
8 changed files with 31 additions and 1 deletions
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1
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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@ -282,6 +282,7 @@ Id EmitBitCount32(EmitContext& ctx, Id value);
Id EmitBitwiseNot32(EmitContext& ctx, Id value); Id EmitBitwiseNot32(EmitContext& ctx, Id value);
Id EmitFindSMsb32(EmitContext& ctx, Id value); Id EmitFindSMsb32(EmitContext& ctx, Id value);
Id EmitFindUMsb32(EmitContext& ctx, Id value); Id EmitFindUMsb32(EmitContext& ctx, Id value);
Id EmitFindILsb32(EmitContext& ctx, Id value);
Id EmitSMin32(EmitContext& ctx, Id a, Id b); Id EmitSMin32(EmitContext& ctx, Id a, Id b);
Id EmitUMin32(EmitContext& ctx, Id a, Id b); Id EmitUMin32(EmitContext& ctx, Id a, Id b);
Id EmitSMax32(EmitContext& ctx, Id a, Id b); Id EmitSMax32(EmitContext& ctx, Id a, Id b);

4
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
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@ -198,6 +198,10 @@ Id EmitFindUMsb32(EmitContext& ctx, Id value) {
return ctx.OpFindUMsb(ctx.U32[1], value); return ctx.OpFindUMsb(ctx.U32[1], value);
} }
Id EmitFindILsb32(EmitContext& ctx, Id value) {
return ctx.OpFindILsb(ctx.U32[1], value);
}
Id EmitSMin32(EmitContext& ctx, Id a, Id b) { Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
return ctx.OpSMin(ctx.U32[1], a, b); return ctx.OpSMin(ctx.U32[1], a, b);
} }

6
src/shader_recompiler/frontend/translate/translate.cpp
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@ -499,6 +499,12 @@ void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_l
case Opcode::V_LSHLREV_B32: case Opcode::V_LSHLREV_B32:
translator.V_LSHLREV_B32(inst); translator.V_LSHLREV_B32(inst);
break; break;
case Opcode::V_LSHL_B32:
translator.V_LSHL_B32(inst);
break;
case Opcode::V_FFBL_B32:
translator.V_FFBL_B32(inst);
break;
case Opcode::V_ADD_I32: case Opcode::V_ADD_I32:
translator.V_ADD_I32(inst); translator.V_ADD_I32(inst);
break; break;

2
src/shader_recompiler/frontend/translate/translate.h
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@ -100,6 +100,7 @@ public:
void V_OR_B32(bool is_xor, const GcnInst& inst); void V_OR_B32(bool is_xor, const GcnInst& inst);
void V_AND_B32(const GcnInst& inst); void V_AND_B32(const GcnInst& inst);
void V_LSHLREV_B32(const GcnInst& inst); void V_LSHLREV_B32(const GcnInst& inst);
void V_LSHL_B32(const GcnInst& inst);
void V_ADD_I32(const GcnInst& inst); void V_ADD_I32(const GcnInst& inst);
void V_ADDC_U32(const GcnInst& inst); void V_ADDC_U32(const GcnInst& inst);
void V_CVT_F32_I32(const GcnInst& inst); void V_CVT_F32_I32(const GcnInst& inst);
@ -161,6 +162,7 @@ public:
void V_LDEXP_F32(const GcnInst& inst); void V_LDEXP_F32(const GcnInst& inst);
void V_CVT_FLR_I32_F32(const GcnInst& inst); void V_CVT_FLR_I32_F32(const GcnInst& inst);
void V_CMP_CLASS_F32(const GcnInst& inst); void V_CMP_CLASS_F32(const GcnInst& inst);
void V_FFBL_B32(const GcnInst& inst);
// Vector Memory // Vector Memory
void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, bool is_format, const GcnInst& inst); void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, bool is_format, const GcnInst& inst);

11
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -91,6 +91,12 @@ void Translator::V_LSHLREV_B32(const GcnInst& inst) {
ir.SetVectorReg(dst_reg, ir.ShiftLeftLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F)))); ir.SetVectorReg(dst_reg, ir.ShiftLeftLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
} }
void Translator::V_LSHL_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
}
void Translator::V_ADD_I32(const GcnInst& inst) { void Translator::V_ADD_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])}; const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))}; const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
@ -601,4 +607,9 @@ void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
} }
} }
void Translator::V_FFBL_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
SetDst(inst.dst[0], ir.FindILsb(src0));
}
} // namespace Shader::Gcn } // namespace Shader::Gcn

6
src/shader_recompiler/ir/ir_emitter.cpp
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@ -278,7 +278,7 @@ Value IREmitter::LoadShared(int bit_size, bool is_signed, const U32& offset) {
case 32: case 32:
return Inst<U32>(Opcode::LoadSharedU32, offset); return Inst<U32>(Opcode::LoadSharedU32, offset);
case 64: case 64:
return Inst<U64>(Opcode::LoadSharedU64, offset); return Inst(Opcode::LoadSharedU64, offset);
case 128: case 128:
return Inst(Opcode::LoadSharedU128, offset); return Inst(Opcode::LoadSharedU128, offset);
default: default:
@ -1088,6 +1088,10 @@ U32 IREmitter::FindUMsb(const U32& value) {
return Inst<U32>(Opcode::FindUMsb32, value); return Inst<U32>(Opcode::FindUMsb32, value);
} }
U32 IREmitter::FindILsb(const U32& value) {
return Inst<U32>(Opcode::FindILsb32, value);
}
U32 IREmitter::SMin(const U32& a, const U32& b) { U32 IREmitter::SMin(const U32& a, const U32& b) {
return Inst<U32>(Opcode::SMin32, a, b); return Inst<U32>(Opcode::SMin32, a, b);
} }

1
src/shader_recompiler/ir/ir_emitter.h
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@ -179,6 +179,7 @@ public:
[[nodiscard]] U32 FindSMsb(const U32& value); [[nodiscard]] U32 FindSMsb(const U32& value);
[[nodiscard]] U32 FindUMsb(const U32& value); [[nodiscard]] U32 FindUMsb(const U32& value);
[[nodiscard]] U32 FindILsb(const U32& value);
[[nodiscard]] U32 SMin(const U32& a, const U32& b); [[nodiscard]] U32 SMin(const U32& a, const U32& b);
[[nodiscard]] U32 UMin(const U32& a, const U32& b); [[nodiscard]] U32 UMin(const U32& a, const U32& b);
[[nodiscard]] U32 IMin(const U32& a, const U32& b, bool is_signed); [[nodiscard]] U32 IMin(const U32& a, const U32& b, bool is_signed);

1
src/shader_recompiler/ir/opcodes.inc
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@ -254,6 +254,7 @@ OPCODE(BitwiseNot32, U32, U32,
OPCODE(FindSMsb32, U32, U32, ) OPCODE(FindSMsb32, U32, U32, )
OPCODE(FindUMsb32, U32, U32, ) OPCODE(FindUMsb32, U32, U32, )
OPCODE(FindILsb32, U32, U32, )
OPCODE(SMin32, U32, U32, U32, ) OPCODE(SMin32, U32, U32, U32, )
OPCODE(UMin32, U32, U32, U32, ) OPCODE(UMin32, U32, U32, U32, )
OPCODE(SMax32, U32, U32, U32, ) OPCODE(SMax32, U32, U32, U32, )