mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
more refactors
This commit is contained in:
Frodo Baggins
parent
3af854539a
commit
8058377e53
@ -380,208 +380,10 @@ static AttributeRegion FindRegionKind(IR::Inst* ring_access, const Shader::Info&
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}
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}
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static IR::Program* g_program; // TODO delete
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struct RingAddressInfo {
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AttributeRegion region{};
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u32 attribute_byte_offset{};
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// For InputCP and OutputCP, offset from the start of the patch's memory (including
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// attribute_byte_offset) For PatchConst, not relevant
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IR::U32 offset_in_patch{IR::Value(0u)};
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};
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class Pass {
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public:
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Pass(Info& info_, RuntimeInfo& runtime_info_) : info(info_), runtime_info(runtime_info_) {
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InitTessConstants(info.tess_consts_ptr_base, info.tess_consts_dword_offset, info,
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runtime_info, tess_constants);
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}
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RingAddressInfo WalkRingAccess(IR::Inst* access, IR::IREmitter& insert_point) {
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Reset();
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RingAddressInfo address_info{};
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IR::Value addr;
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switch (access->GetOpcode()) {
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case IR::Opcode::LoadSharedU32:
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case IR::Opcode::LoadSharedU64:
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case IR::Opcode::LoadSharedU128:
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case IR::Opcode::WriteSharedU32:
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case IR::Opcode::WriteSharedU64:
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case IR::Opcode::WriteSharedU128:
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addr = access->Arg(0);
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break;
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case IR::Opcode::StoreBufferU32:
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4:
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addr = access->Arg(1);
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break;
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default:
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UNREACHABLE();
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}
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products.emplace_back(addr);
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Visit(addr);
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FindIndexInfo(address_info, insert_point);
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return address_info;
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}
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private:
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void Reset() {
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within_mul = false;
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products.clear();
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}
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void Visit(IR::Value node) {
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IR::Value a, b, c;
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if (MakeInstPattern<IR::Opcode::IMul32>(MatchValue(a), MatchValue(b)).DoMatch(node)) {
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bool saved_within_mul = within_mul;
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within_mul = true;
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Visit(a);
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Visit(b);
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within_mul = saved_within_mul;
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} else if (MakeInstPattern<IR::Opcode::IAdd32>(MatchValue(a), MatchValue(b))
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.DoMatch(node)) {
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if (within_mul) {
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UNREACHABLE_MSG("Test");
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products.back().as_factors.emplace_back(IR::U32{node});
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} else {
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products.back().as_nested_value = IR::U32{a};
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Visit(a);
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products.emplace_back(b);
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Visit(b);
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}
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} else if (MakeInstPattern<IR::Opcode::ShiftLeftLogical32>(MatchValue(a), MatchImm(b))
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.DoMatch(node)) {
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products.back().as_factors.emplace_back(IR::Value(u32(2 << (b.U32() - 1))));
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Visit(a);
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} else if (MakeInstPattern<IR::Opcode::GetAttributeU32>(MatchValue(a), MatchU32(0))
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.DoMatch(node)) {
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products.back().as_factors.emplace_back(a.Attribute());
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} else if (MakeInstPattern<IR::Opcode::GetAttributeU32>(MatchValue(a), MatchU32(0))
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.DoMatch(node)) {
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products.back().as_factors.emplace_back(a);
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} else if (MakeInstPattern<IR::Opcode::BitFieldSExtract>(MatchValue(a), MatchIgnore(),
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MatchIgnore())
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.DoMatch(node)) {
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Visit(a);
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} else if (MakeInstPattern<IR::Opcode::BitFieldUExtract>(MatchValue(a), MatchIgnore(),
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MatchIgnore())
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.DoMatch(node)) {
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Visit(a);
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} else if (MakeInstPattern<IR::Opcode::BitCastF32U32>(MatchValue(a)).DoMatch(node)) {
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return Visit(a);
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} else if (MakeInstPattern<IR::Opcode::BitCastU32F32>(MatchValue(a)).DoMatch(node)) {
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return Visit(a);
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} else if (node.TryInstRecursive() &&
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node.InstRecursive()->GetOpcode() == IR::Opcode::Phi) {
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DEBUG_ASSERT(false && "Phi test");
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products.back().as_factors.emplace_back(node);
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} else {
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products.back().as_factors.emplace_back(node);
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}
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}
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void FindIndexInfo(RingAddressInfo& address_info, IR::IREmitter& ir) {
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// infer which attribute base the address is indexing
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// by how many addends are multiplied by TessellationDataConstantBuffer::m_hsNumPatch.
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// Also handle m_hsOutputBase or m_patchConstBase
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u32 region_count = 0;
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// Remove addends except for the attribute offset and possibly the
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// control point index calc
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std::erase_if(products, [&](Product& p) {
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for (IR::Value& value : p.as_factors) {
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if (value.Type() == IR::Type::Attribute) {
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if (value.Attribute() == IR::Attribute::TcsNumPatches ||
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value.Attribute() == IR::Attribute::TcsOutputBase) {
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++region_count;
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return true;
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} else if (value.Attribute() == IR::Attribute::TcsPatchConstBase) {
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region_count += 2;
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return true;
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} else if (value.Attribute() == IR::Attribute::TessPatchIdInVgt) {
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return true;
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}
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}
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}
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return false;
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});
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// DumpIR(*g_program, "before_crash");
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// Look for some term with a dynamic index (should be the control point index)
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for (auto i = 0; i < products.size(); i++) {
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auto& factors = products[i].as_factors;
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// Remember this as the index term
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if (std::any_of(factors.begin(), factors.end(), [&](const IR::Value& v) {
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return !v.IsImmediate() || v.Type() == IR::Type::Attribute;
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})) {
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address_info.offset_in_patch =
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ir.IAdd(address_info.offset_in_patch, products[i].as_nested_value);
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} else {
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ASSERT_MSG(factors.size() == 1, "factors all const but not const folded");
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// Otherwise assume it contributes to the attribute
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address_info.offset_in_patch =
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ir.IAdd(address_info.offset_in_patch, IR::U32{factors[0]});
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address_info.attribute_byte_offset += factors[0].U32();
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}
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}
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if (region_count == 0) {
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address_info.region = AttributeRegion::InputCP;
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} else if (info.l_stage == LogicalStage::TessellationControl &&
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runtime_info.hs_info.IsPassthrough()) {
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ASSERT(region_count <= 1);
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address_info.region = AttributeRegion::PatchConst;
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} else {
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ASSERT(region_count <= 2);
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address_info.region = AttributeRegion(region_count);
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}
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}
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Info& info;
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RuntimeInfo& runtime_info;
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TessellationDataConstantBuffer tess_constants;
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bool within_mul{};
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// One product in the sum of products making up an address
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struct Product {
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Product(IR::Value val_) : as_nested_value(val_), as_factors() {}
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Product(const Product& other) = default;
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~Product() = default;
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// IR value used as an addend in address calc
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IR::U32 as_nested_value;
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// all the leaves that feed the multiplication, linear
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// TODO small_vector
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// boost::container::small_vector<IR::Value, 4> as_factors;
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std::vector<IR::Value> as_factors;
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};
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std::vector<Product> products;
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};
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} // namespace
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void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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TessConstantUseWalker walker;
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g_program = &program; // TODO delete
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Info& info = program.info;
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Pass pass(info, runtime_info);
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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walker.MarkTessAttributeUsers(&inst);
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}
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}
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}
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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@ -646,7 +448,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::WriteSharedU32:
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case IR::Opcode::WriteSharedU64: {
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// DumpIR(program, "before_walk");
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RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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// RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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const u32 num_dwords = opcode == IR::Opcode::WriteSharedU32
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? 1
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@ -669,7 +471,6 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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}
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if (output_kind == AttributeRegion::OutputCP) {
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#if 0
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// Invocation ID array index is implicit, handled by SPIRV backend
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IR::U32 attr_index = ir.ShiftRightLogical(
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ir.IMod(addr, ir.GetAttributeU32(IR::Attribute::TcsCpStride)),
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@ -677,17 +478,11 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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IR::U32 comp_index =
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ir.ShiftRightLogical(ir.BitwiseAnd(addr, ir.Imm32(0xFU)), ir.Imm32(2u));
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ir.SetTcsGenericAttribute(data, attr_index, comp_index);
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#else
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u32 offset_dw = address_info.attribute_byte_offset >> 2;
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const u32 param = offset_dw >> 2;
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const u32 comp = offset_dw & 3;
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// Invocation ID array index is implicit, handled by SPIRV backend
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ir.SetTcsGenericAttribute(data, ir.Imm32(param), ir.Imm32(comp));
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#endif
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} else {
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ASSERT(output_kind == AttributeRegion::PatchConst);
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ir.SetPatch(IR::PatchGeneric(address_info.attribute_byte_offset >> 2),
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data);
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ASSERT_MSG(addr.IsImmediate(), "patch addr non imm, inst {}",
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fmt::ptr(addr.Inst()));
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ir.SetPatch(IR::PatchGeneric(addr.U32() >> 2), data);
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}
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};
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@ -704,20 +499,21 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::LoadSharedU32: {
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// case IR::Opcode::LoadSharedU64:
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// case IR::Opcode::LoadSharedU128:
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RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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const IR::U32 addr{inst.Arg(0)};
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AttributeRegion region = FindRegionKind(&inst, info, runtime_info);
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ASSERT(address_info.region == AttributeRegion::InputCP ||
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address_info.region == AttributeRegion::OutputCP);
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switch (address_info.region) {
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ASSERT(region == AttributeRegion::InputCP || region == AttributeRegion::OutputCP);
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switch (region) {
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case AttributeRegion::InputCP: {
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u32 offset_dw =
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(address_info.attribute_byte_offset % runtime_info.hs_info.ls_stride) >> 2;
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const u32 attr_no = offset_dw >> 2;
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const u32 comp = offset_dw & 3;
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IR::U32 control_point_index = ir.IDiv(IR::U32{address_info.offset_in_patch},
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ir.Imm32(runtime_info.hs_info.ls_stride));
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IR::Value attr_read = ir.GetTessGenericAttribute(
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control_point_index, ir.Imm32(attr_no), ir.Imm32(comp));
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IR::U32 control_point_index =
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ir.IDiv(addr, ir.Imm32(runtime_info.hs_info.ls_stride));
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IR::U32 attr_index = ir.ShiftRightLogical(
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ir.IMod(addr, ir.GetAttributeU32(IR::Attribute::TcsLsStride)),
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ir.Imm32(4u));
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IR::U32 comp_index =
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ir.ShiftRightLogical(ir.BitwiseAnd(addr, ir.Imm32(0xFU)), ir.Imm32(2u));
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IR::Value attr_read =
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ir.GetTessGenericAttribute(control_point_index, attr_index, comp_index);
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attr_read = ir.BitCast<IR::U32>(IR::F32{attr_read});
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inst.ReplaceUsesWithAndRemove(attr_read);
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break;
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@ -775,17 +571,7 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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// TODO refactor
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void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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TessConstantUseWalker walker;
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Info& info = program.info;
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Pass pass(info, runtime_info);
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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walker.MarkTessAttributeUsers(&inst);
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}
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}
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}
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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@ -795,8 +581,7 @@ void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::LoadSharedU32: {
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// case IR::Opcode::LoadSharedU64:
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// case IR::Opcode::LoadSharedU128: // TODO
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RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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const IR::U32 addr = IR::U32{inst.Arg(0)};
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const IR::U32 addr{inst.Arg(0)};
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AttributeRegion region = FindRegionKind(&inst, info, runtime_info);
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ASSERT(region == AttributeRegion::OutputCP ||
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@ -817,9 +602,10 @@ void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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break;
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}
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case AttributeRegion::PatchConst: {
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// TODO make patch consts into dynamic offset
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u32 offset_dw = address_info.attribute_byte_offset >> 2;
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IR::Value get_patch = ir.GetPatch(IR::PatchGeneric(offset_dw));
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// TODO if assert fails then make patch consts into dynamic offset
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ASSERT_MSG(addr.IsImmediate(), "patch addr non imm, inst {}",
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fmt::ptr(addr.Inst()));
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IR::Value get_patch = ir.GetPatch(IR::PatchGeneric(addr.U32() >> 2));
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inst.ReplaceUsesWithAndRemove(get_patch);
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break;
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}
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@ -963,6 +749,38 @@ void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
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}
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}
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}
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TessConstantUseWalker walker;
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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walker.MarkTessAttributeUsers(&inst);
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}
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}
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}
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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switch (inst.Arg(0).Attribute()) {
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// Should verify that these are only used in address calculations for attr
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// read/write
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// Replace with 0 so we can dynamically index the control points within the
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// region allocated for this patch (input or output). These terms should only
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// contribute to the base address of that region, so replacing with 0 *should*
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// be fine
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case IR::Attribute::TcsNumPatches:
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case IR::Attribute::TcsOutputBase:
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case IR::Attribute::TcsPatchConstBase:
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case IR::Attribute::TessPatchIdInVgt:
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inst.ReplaceUsesWithAndRemove(IR::Value(0u));
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break;
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default:
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break;
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}
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}
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}
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}
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}
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void TessellationPostprocess(IR::Program& program, RuntimeInfo& runtime_info) {
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@ -982,21 +800,6 @@ void TessellationPostprocess(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Attribute::TcsCpStride:
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inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.m_hsCpStride));
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break;
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// Should verify that these are only used in address calculations for attr
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// read/write
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// Replace with 0 so we can dynamically index the control points within the
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// region allocated for this patch (input or output). These terms should only
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// contribute to the base address of that region, so replacing with 0 *should*
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// be fine
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case IR::Attribute::TcsNumPatches:
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case IR::Attribute::TcsOutputBase:
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case IR::Attribute::TcsPatchConstBase:
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case IR::Attribute::TessPatchIdInVgt:
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inst.ReplaceUsesWithAndRemove(IR::Value(0u));
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break;
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case IR::Attribute::TcsPatchConstSize:
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case IR::Attribute::TcsPatchOutputSize:
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case IR::Attribute::TcsFirstEdgeTessFactorIndex:
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default:
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break;
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}
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