mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
handle other registers as well
This commit is contained in:
parent
dcf659735e
commit
81a5062ee9
@ -53,28 +53,73 @@ void Translator::EmitPrologue() {
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}
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}
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break;
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break;
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case Stage::Fragment:
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case Stage::Fragment:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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dst_vreg = IR::VectorReg::V0;
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// The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
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if (runtime_info.fs_info.addr_flags.persp_sample_ena) {
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// cases it will be only those two, but if shader is using both e.g linear and perspective
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++dst_vreg; // I
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// inputs it can be more For now assume that this isn't the case.
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++dst_vreg; // J
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dst_vreg = IR::VectorReg::V2;
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for (u32 i = 0; i < 4; i++) {
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if (True(runtime_info.fs_info.addr_flags & Shader::PsInputFlags(1 << i))) {
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if (True(runtime_info.fs_info.en_flags & Shader::PsInputFlags(1 << i))) {
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ir.SetVectorReg(dst_vreg, ir.GetAttribute(IR::Attribute::FragCoord, i));
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} else {
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ir.SetVectorReg(dst_vreg, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.persp_center_ena) {
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++dst_vreg; // I
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++dst_vreg; // J
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}
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if (runtime_info.fs_info.addr_flags.persp_centroid_ena) {
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++dst_vreg; // I
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++dst_vreg; // J
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}
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if (runtime_info.fs_info.addr_flags.persp_pull_model_ena) {
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++dst_vreg; // I/W
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++dst_vreg; // J/W
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++dst_vreg; // 1/W
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}
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if (runtime_info.fs_info.addr_flags.linear_sample_ena) {
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++dst_vreg; // I
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++dst_vreg; // J
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}
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if (runtime_info.fs_info.addr_flags.linear_center_ena) {
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++dst_vreg; // I
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++dst_vreg; // J
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}
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if (runtime_info.fs_info.addr_flags.linear_centroid_ena) {
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++dst_vreg; // I
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++dst_vreg; // J
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}
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if (runtime_info.fs_info.addr_flags.line_stipple_tex_ena) {
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++dst_vreg;
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++dst_vreg;
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}
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_x_float_ena) {
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if (True(runtime_info.fs_info.addr_flags & Shader::PsInputFlags::FrontFacing)) {
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if (runtime_info.fs_info.en_flags.pos_x_float_ena) {
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if (True(runtime_info.fs_info.en_flags & Shader::PsInputFlags::FrontFacing)) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 0));
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ir.SetVectorReg(dst_vreg, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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} else {
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} else {
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ir.SetVectorReg(dst_vreg, ir.Imm32(0));
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_y_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_y_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 1));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_z_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_z_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 2));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_w_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_w_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 3));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.front_face_ena) {
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if (runtime_info.fs_info.en_flags.front_face_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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++dst_vreg;
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}
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}
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break;
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break;
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case Stage::Compute:
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case Stage::Compute:
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@ -7,6 +7,7 @@
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#include <span>
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#include <span>
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#include <boost/container/static_vector.hpp>
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#include <boost/container/static_vector.hpp>
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#include "common/types.h"
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#include "common/types.h"
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#include "video_core/amdgpu/liverpool.h"
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#include "video_core/amdgpu/types.h"
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#include "video_core/amdgpu/types.h"
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namespace Shader {
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namespace Shader {
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@ -96,16 +97,6 @@ enum class MrtSwizzle : u8 {
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};
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};
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static constexpr u32 MaxColorBuffers = 8;
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static constexpr u32 MaxColorBuffers = 8;
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enum class PsInputFlags : u8 {
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None = 0,
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PosX = 1 << 0,
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PosY = 1 << 1,
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PosZ = 1 << 2,
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PosW = 1 << 3,
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FrontFacing = 1 << 4,
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};
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DECLARE_ENUM_FLAG_OPERATORS(PsInputFlags)
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struct FragmentRuntimeInfo {
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struct FragmentRuntimeInfo {
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struct PsInput {
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struct PsInput {
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u8 param_index;
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u8 param_index;
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@ -115,8 +106,8 @@ struct FragmentRuntimeInfo {
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auto operator<=>(const PsInput&) const noexcept = default;
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auto operator<=>(const PsInput&) const noexcept = default;
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};
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};
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PsInputFlags en_flags;
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AmdGpu::Liverpool::PsInput en_flags;
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PsInputFlags addr_flags;
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AmdGpu::Liverpool::PsInput addr_flags;
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u32 num_inputs;
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u32 num_inputs;
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std::array<PsInput, 32> inputs;
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std::array<PsInput, 32> inputs;
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struct PsColorBuffer {
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struct PsColorBuffer {
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@ -129,7 +120,7 @@ struct FragmentRuntimeInfo {
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bool operator==(const FragmentRuntimeInfo& other) const noexcept {
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bool operator==(const FragmentRuntimeInfo& other) const noexcept {
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return std::ranges::equal(color_buffers, other.color_buffers) &&
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return std::ranges::equal(color_buffers, other.color_buffers) &&
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en_flags == other.en_flags && addr_flags == other.addr_flags &&
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en_flags.raw == other.en_flags.raw && addr_flags.raw == other.addr_flags.raw &&
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num_inputs == other.num_inputs &&
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num_inputs == other.num_inputs &&
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std::ranges::equal(inputs.begin(), inputs.begin() + num_inputs, other.inputs.begin(),
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std::ranges::equal(inputs.begin(), inputs.begin() + num_inputs, other.inputs.begin(),
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other.inputs.begin() + num_inputs);
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other.inputs.begin() + num_inputs);
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@ -1071,7 +1071,9 @@ struct Liverpool {
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BitField<27, 1, u32> enable_postz_overrasterization;
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BitField<27, 1, u32> enable_postz_overrasterization;
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};
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};
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struct PsInput {
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union PsInput {
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u32 raw;
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struct {
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u32 persp_sample_ena : 1;
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u32 persp_sample_ena : 1;
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u32 persp_center_ena : 1;
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u32 persp_center_ena : 1;
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u32 persp_centroid_ena : 1;
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u32 persp_centroid_ena : 1;
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@ -1089,6 +1091,7 @@ struct Liverpool {
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u32 sample_coverage_ena : 1;
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u32 sample_coverage_ena : 1;
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u32 pos_fixed_pt_ena : 1;
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u32 pos_fixed_pt_ena : 1;
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};
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};
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};
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union Regs {
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union Regs {
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struct {
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struct {
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@ -123,28 +123,8 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
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}
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}
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case Shader::Stage::Fragment: {
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case Shader::Stage::Fragment: {
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BuildCommon(regs.ps_program);
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BuildCommon(regs.ps_program);
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info.fs_info.en_flags =
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info.fs_info.en_flags = regs.ps_input_ena;
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(regs.ps_input_ena.pos_x_float_ena ? Shader::PsInputFlags::PosX
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info.fs_info.addr_flags = regs.ps_input_addr;
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: Shader::PsInputFlags::None) |
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(regs.ps_input_ena.pos_y_float_ena ? Shader::PsInputFlags::PosY
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: Shader::PsInputFlags::None) |
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(regs.ps_input_ena.pos_z_float_ena ? Shader::PsInputFlags::PosZ
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: Shader::PsInputFlags::None) |
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(regs.ps_input_ena.pos_w_float_ena ? Shader::PsInputFlags::PosW
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: Shader::PsInputFlags::None) |
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(regs.ps_input_ena.front_face_ena ? Shader::PsInputFlags::FrontFacing
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: Shader::PsInputFlags::None);
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info.fs_info.addr_flags =
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(regs.ps_input_addr.pos_x_float_ena ? Shader::PsInputFlags::PosX
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: Shader::PsInputFlags::None) |
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(regs.ps_input_addr.pos_y_float_ena ? Shader::PsInputFlags::PosY
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: Shader::PsInputFlags::None) |
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(regs.ps_input_addr.pos_z_float_ena ? Shader::PsInputFlags::PosZ
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: Shader::PsInputFlags::None) |
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(regs.ps_input_addr.pos_w_float_ena ? Shader::PsInputFlags::PosW
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: Shader::PsInputFlags::None) |
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(regs.ps_input_addr.front_face_ena ? Shader::PsInputFlags::FrontFacing
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: Shader::PsInputFlags::None);
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const auto& ps_inputs = regs.ps_inputs;
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const auto& ps_inputs = regs.ps_inputs;
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info.fs_info.num_inputs = regs.num_interp;
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info.fs_info.num_inputs = regs.num_interp;
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for (u32 i = 0; i < regs.num_interp; i++) {
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for (u32 i = 0; i < regs.num_interp; i++) {
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