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Implement V_CMP_GT_U64 (#3352)

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* Implement V_CMP_GT_U64

* Add GroupAny

* Use GroupAny

* Add assert

* clang
This commit is contained in:
kalaposfos13
2025-08-21 04:53:54 +02:00
committed by GitHub
parent 2d98adef17
commit 8a84f1b778
6 changed files with 20 additions and 0 deletions
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1
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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@@ -536,6 +536,7 @@ Id EmitReadLane(EmitContext& ctx, Id value, Id lane);
Id EmitWriteLane(EmitContext& ctx, Id value, Id write_value, u32 lane); Id EmitWriteLane(EmitContext& ctx, Id value, Id write_value, u32 lane);
Id EmitBallot(EmitContext& ctx, Id bit); Id EmitBallot(EmitContext& ctx, Id bit);
Id EmitBallotFindLsb(EmitContext& ctx, Id mask); Id EmitBallotFindLsb(EmitContext& ctx, Id mask);
Id EmitGroupAny(EmitContext& ctx, Id bit);
Id EmitDataAppend(EmitContext& ctx, u32 gds_addr, u32 binding); Id EmitDataAppend(EmitContext& ctx, u32 gds_addr, u32 binding);
Id EmitDataConsume(EmitContext& ctx, u32 gds_addr, u32 binding); Id EmitDataConsume(EmitContext& ctx, u32 gds_addr, u32 binding);

4
src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
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@@ -42,4 +42,8 @@ Id EmitBallotFindLsb(EmitContext& ctx, Id mask) {
return ctx.OpGroupNonUniformBallotFindLSB(ctx.U32[1], SubgroupScope(ctx), mask); return ctx.OpGroupNonUniformBallotFindLSB(ctx.U32[1], SubgroupScope(ctx), mask);
} }
Id EmitGroupAny(EmitContext& ctx, Id bit) {
return ctx.OpGroupNonUniformAny(ctx.U1[1], SubgroupScope(ctx), bit);
}
} // namespace Shader::Backend::SPIRV } // namespace Shader::Backend::SPIRV

8
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@@ -331,6 +331,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_CMP_U64(ConditionOp::EQ, false, false, inst); return V_CMP_U64(ConditionOp::EQ, false, false, inst);
case Opcode::V_CMP_NE_U64: case Opcode::V_CMP_NE_U64:
return V_CMP_U64(ConditionOp::LG, false, false, inst); return V_CMP_U64(ConditionOp::LG, false, false, inst);
case Opcode::V_CMP_GT_U64:
return V_CMP_U64(ConditionOp::GT, false, false, inst);
case Opcode::V_CMP_CLASS_F32: case Opcode::V_CMP_CLASS_F32:
return V_CMP_CLASS_F32(inst); return V_CMP_CLASS_F32(inst);
@@ -1020,6 +1022,12 @@ void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const
return ir.IEqual(src0, src1); return ir.IEqual(src0, src1);
case ConditionOp::LG: // NE case ConditionOp::LG: // NE
return ir.INotEqual(src0, src1); return ir.INotEqual(src0, src1);
case ConditionOp::GT:
if (src1.IsImmediate() && src1.U64() == 0) {
ASSERT(inst.src[0].field == OperandField::ScalarGPR);
return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)));
}
return ir.IGreaterThan(src0, src1, is_signed);
default: default:
UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op)); UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
} }

5
src/shader_recompiler/ir/ir_emitter.cpp
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@@ -5,6 +5,7 @@
#include <source_location> #include <source_location>
#include <boost/container/small_vector.hpp> #include <boost/container/small_vector.hpp>
#include "common/assert.h" #include "common/assert.h"
#include "ir_emitter.h"
#include "shader_recompiler/exception.h" #include "shader_recompiler/exception.h"
#include "shader_recompiler/ir/debug_print.h" #include "shader_recompiler/ir/debug_print.h"
#include "shader_recompiler/ir/ir_emitter.h" #include "shader_recompiler/ir/ir_emitter.h"
@@ -668,6 +669,10 @@ U32 IREmitter::BallotFindLsb(const Value& mask) {
return Inst<U32>(Opcode::BallotFindLsb, mask); return Inst<U32>(Opcode::BallotFindLsb, mask);
} }
U1 IREmitter::GroupAny(const U1& bit) {
return Inst<U1>(Opcode::GroupAny, bit);
}
F32F64 IREmitter::FPAdd(const F32F64& a, const F32F64& b) { F32F64 IREmitter::FPAdd(const F32F64& a, const F32F64& b) {
if (a.Type() != b.Type()) { if (a.Type() != b.Type()) {
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type()); UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());

1
src/shader_recompiler/ir/ir_emitter.h
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@@ -177,6 +177,7 @@ public:
[[nodiscard]] U32 WriteLane(const U32& value, const U32& write_value, const U32& lane); [[nodiscard]] U32 WriteLane(const U32& value, const U32& write_value, const U32& lane);
[[nodiscard]] Value Ballot(const U1& bit); [[nodiscard]] Value Ballot(const U1& bit);
[[nodiscard]] U32 BallotFindLsb(const Value& mask); [[nodiscard]] U32 BallotFindLsb(const Value& mask);
[[nodiscard]] U1 GroupAny(const U1& bit);
[[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2); [[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2);
[[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2, const Value& e3); [[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2, const Value& e3);

1
src/shader_recompiler/ir/opcodes.inc
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@@ -479,3 +479,4 @@ OPCODE(Ballot, U32x4, U1,
OPCODE(BallotFindLsb, U32, U32x4, ) OPCODE(BallotFindLsb, U32, U32x4, )
OPCODE(DataAppend, U32, U32, U32 ) OPCODE(DataAppend, U32, U32, U32 )
OPCODE(DataConsume, U32, U32, U32 ) OPCODE(DataConsume, U32, U32, U32 )
OPCODE(GroupAny, U1, U1, )