From 3a06c40f2fc2b06b019492b9c747178f2326e5da Mon Sep 17 00:00:00 2001 From: Andrew Middendorp <72170013+amiddendorp22@users.noreply.github.com> Date: Sat, 7 Sep 2024 11:16:11 -0700 Subject: [PATCH 1/4] Update src/shader_recompiler/frontend/translate/scalar_alu.cpp Co-authored-by: baggins183 --- src/shader_recompiler/frontend/translate/scalar_alu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index 56de5afda..ac64306f6 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -389,7 +389,7 @@ void Translator::S_AND_B32(NegateMode negate, const GcnInst& inst) { const IR::U32 src0{GetSrc(inst.src[0])}; IR::U32 src1{GetSrc(inst.src[1])}; if (negate == NegateMode::Src1) { - IR::U32 src1{ir.BitwiseNot(GetSrc(inst.src[1]))}; + src1 = ir.BitwiseNot(GetSrc(inst.src[1])); } IR::U32 result{ir.BitwiseAnd(src0, src1)}; if (negate == NegateMode::Result) { From a88750eea8d318e411a9cb245980a3879624fb1e Mon Sep 17 00:00:00 2001 From: Andrew Middendorp <72170013+amiddendorp22@users.noreply.github.com> Date: Sat, 7 Sep 2024 11:16:39 -0700 Subject: [PATCH 2/4] Fix result and src1 Co-authored-by: baggins183 --- src/shader_recompiler/frontend/translate/scalar_alu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index ac64306f6..449b6f27b 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -393,7 +393,7 @@ void Translator::S_AND_B32(NegateMode negate, const GcnInst& inst) { } IR::U32 result{ir.BitwiseAnd(src0, src1)}; if (negate == NegateMode::Result) { - IR::U32 result{ir.BitwiseNot(ir.BitwiseAnd(src0, src1))}; + result = ir.BitwiseNot(ir.BitwiseAnd(src0, src1)); } SetDst(inst.dst[0], result); ir.SetScc(ir.INotEqual(result, ir.Imm32(0))); From f0f8f9c1c7c9fd8d1dd137622385bd8a287dfe48 Mon Sep 17 00:00:00 2001 From: Andrew Middendorp <72170013+amiddendorp22@users.noreply.github.com> Date: Sat, 7 Sep 2024 12:32:46 -0700 Subject: [PATCH 3/4] update result Co-authored-by: baggins183 --- src/shader_recompiler/frontend/translate/scalar_alu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index 449b6f27b..3d00190c6 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -393,7 +393,7 @@ void Translator::S_AND_B32(NegateMode negate, const GcnInst& inst) { } IR::U32 result{ir.BitwiseAnd(src0, src1)}; if (negate == NegateMode::Result) { - result = ir.BitwiseNot(ir.BitwiseAnd(src0, src1)); + result = ir.BitwiseNot(result); } SetDst(inst.dst[0], result); ir.SetScc(ir.INotEqual(result, ir.Imm32(0))); From d70ef9b6e8a13377812fbc03b6a2cc62127c7a6f Mon Sep 17 00:00:00 2001 From: Andrew Middendorp <72170013+amiddendorp22@users.noreply.github.com> Date: Sat, 7 Sep 2024 12:32:59 -0700 Subject: [PATCH 4/4] Update src1 Co-authored-by: baggins183 --- src/shader_recompiler/frontend/translate/scalar_alu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index 3d00190c6..5b194db88 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -389,7 +389,7 @@ void Translator::S_AND_B32(NegateMode negate, const GcnInst& inst) { const IR::U32 src0{GetSrc(inst.src[0])}; IR::U32 src1{GetSrc(inst.src[1])}; if (negate == NegateMode::Src1) { - src1 = ir.BitwiseNot(GetSrc(inst.src[1])); + src1 = ir.BitwiseNot(src1); } IR::U32 result{ir.BitwiseAnd(src0, src1)}; if (negate == NegateMode::Result) {