mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
save work probably broken and slow
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parent
2078da1f6d
commit
8d53b6956f
@ -461,7 +461,6 @@ private:
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Visit(a);
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} else if (MakeInstPattern<IR::Opcode::GetAttributeU32>(MatchValue(a), MatchU32(0))
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.DoMatch(node)) {
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printf("here\n");
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products.back().as_factors.emplace_back(a.Attribute());
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} else if (MakeInstPattern<IR::Opcode::GetAttributeU32>(MatchValue(a), MatchU32(0))
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.DoMatch(node)) {
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@ -571,10 +570,19 @@ private:
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} // namespace
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void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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TessConstantUseWalker walker;
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g_program = &program; // TODO delete
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Info& info = program.info;
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Pass pass(info, runtime_info);
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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walker.MarkTessAttributeUsers(&inst);
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}
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}
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}
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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IR::IREmitter ir{*block,
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@ -585,9 +593,6 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4: {
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// TODO: rename struct
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RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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const auto info = inst.Flags<IR::BufferInstInfo>();
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if (!info.globally_coherent) {
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break;
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@ -600,8 +605,10 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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return ir.BitCast<IR::F32, IR::U32>(IR::U32{data});
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};
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const u32 num_dwords = u32(opcode) - u32(IR::Opcode::StoreBufferU32) + 1;
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const u32 gcn_factor_idx =
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(info.inst_offset.Value() + address_info.attribute_byte_offset) >> 2;
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IR::U32 index = IR::U32{inst.Arg(1)};
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// ASSERT(index.IsImmediate());
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// const u32 gcn_factor_idx = (info.inst_offset.Value() + index.U32()) >> 2;
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const u32 gcn_factor_idx = (info.inst_offset.Value()) >> 2;
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const IR::Value data = inst.Arg(2);
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auto get_factor_attr = [&](u32 gcn_factor_idx) -> IR::Patch {
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@ -645,8 +652,8 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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const u32 num_dwords = opcode == IR::Opcode::WriteSharedU32
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? 1
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: (opcode == IR::Opcode::WriteSharedU64 ? 2 : 4);
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const IR::U32 addr = IR::U32{inst.Arg(0)};
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const IR::Value data = inst.Arg(1);
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const IR::U32 addr{inst.Arg(0)};
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const IR::U32 data{inst.Arg(1)};
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const auto [data_lo, data_hi] = [&] -> std::pair<IR::U32, IR::U32> {
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if (num_dwords == 1) {
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return {IR::U32{data}, IR::U32{}};
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@ -655,14 +662,15 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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return {IR::U32{prod->Arg(0)}, IR::U32{prod->Arg(1)}};
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}();
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const auto SetOutput = [&](IR::U32 value, u32 offset_dw,
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AttributeRegion output_kind) {
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const auto SetOutput = [&](IR::U32 addr, IR::U32 value, AttributeRegion output_kind,
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u32 off_dw = 0) {
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const IR::F32 data = ir.BitCast<IR::F32, IR::U32>(value);
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if (off_dw > 0) {
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addr = ir.IAdd(addr, ir.Imm32(off_dw));
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}
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if (output_kind == AttributeRegion::OutputCP) {
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const u32 attr_no = offset_dw >> 2;
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const u32 comp = offset_dw & 3;
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// Invocation ID array index is implicit, handled by SPIRV backend
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// ir.SetAttribute(IR::Attribute::Param0 + param, data, comp);
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IR::U32 attr_index = ir.ShiftRightLogical(
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ir.IMod(addr, ir.GetAttributeU32(IR::Attribute::TcsCpStride)),
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ir.Imm32(4u));
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@ -671,18 +679,18 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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ir.SetTcsGenericAttribute(data, attr_index, comp_index);
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} else {
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ASSERT(output_kind == AttributeRegion::PatchConst);
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ir.SetPatch(IR::PatchGeneric(offset_dw), data);
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ir.SetPatch(IR::PatchGeneric(address_info.attribute_byte_offset >> 2),
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data);
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}
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};
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u32 offset_dw = address_info.attribute_byte_offset >> 2;
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SetOutput(data_lo, offset_dw, address_info.region);
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AttributeRegion region = FindRegionKind(&inst, info, runtime_info);
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SetOutput(addr, data, region);
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if (num_dwords > 1) {
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// TODO handle WriteSharedU128
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SetOutput(data_hi, offset_dw + 1, address_info.region);
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SetOutput(addr, data_hi, region, 1);
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}
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inst.Invalidate();
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break;
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}
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@ -760,9 +768,18 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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// TODO refactor
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void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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TessConstantUseWalker walker;
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Info& info = program.info;
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Pass pass(info, runtime_info);
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (inst.GetOpcode() == IR::Opcode::GetAttributeU32) {
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walker.MarkTessAttributeUsers(&inst);
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}
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}
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}
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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@ -773,19 +790,14 @@ void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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// case IR::Opcode::LoadSharedU128: // TODO
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RingAddressInfo address_info = pass.WalkRingAccess(&inst, ir);
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const IR::U32 addr = IR::U32{inst.Arg(0)};
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AttributeRegion region = FindRegionKind(&inst, info, runtime_info);
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ASSERT(address_info.region == AttributeRegion::OutputCP ||
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address_info.region == AttributeRegion::PatchConst);
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switch (address_info.region) {
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ASSERT(region == AttributeRegion::OutputCP ||
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region == AttributeRegion::PatchConst);
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switch (region) {
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case AttributeRegion::OutputCP: {
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u32 offset_dw = (address_info.attribute_byte_offset %
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runtime_info.vs_info.hs_output_cp_stride) >>
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2;
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const u32 attr_no = offset_dw >> 2;
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const u32 comp = offset_dw & 3;
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IR::U32 control_point_index =
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ir.IDiv(IR::U32{address_info.offset_in_patch},
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ir.Imm32(runtime_info.vs_info.hs_output_cp_stride));
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ir.IDiv(addr, ir.Imm32(runtime_info.vs_info.hs_output_cp_stride));
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IR::U32 attr_index = ir.ShiftRightLogical(
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ir.IMod(addr, ir.GetAttributeU32(IR::Attribute::TcsCpStride)),
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ir.Imm32(4u));
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@ -798,6 +810,7 @@ void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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break;
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}
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case AttributeRegion::PatchConst: {
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// TODO make patch consts into dynamic offset
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u32 offset_dw = address_info.attribute_byte_offset >> 2;
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IR::Value get_patch = ir.GetPatch(IR::PatchGeneric(offset_dw));
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inst.ReplaceUsesWithAndRemove(get_patch);
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