From ab158fd4d763e1b51ccc32bde5ab19f4e7cb0a1d Mon Sep 17 00:00:00 2001 From: Lander Gallastegi Date: Mon, 7 Apr 2025 23:04:34 +0200 Subject: [PATCH] Don't reuse stack space for now --- .../backend/asm_x64/x64_emit_context.cpp | 23 +++---------------- .../backend/asm_x64/x64_emit_context.h | 2 -- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/shader_recompiler/backend/asm_x64/x64_emit_context.cpp b/src/shader_recompiler/backend/asm_x64/x64_emit_context.cpp index ee104fe89..7d8449f53 100644 --- a/src/shader_recompiler/backend/asm_x64/x64_emit_context.cpp +++ b/src/shader_recompiler/backend/asm_x64/x64_emit_context.cpp @@ -167,12 +167,7 @@ void EmitContext::SpillInst(RegAllocContext& ctx, const ActiveInstInterval& inte ActiveIntervalList& active_intervals) { const auto get_operand = [&](IR::Inst* inst) -> Operand { size_t current_sp = inst_stack_space; - if (ctx.free_stack_slots.empty()) { - inst_stack_space += 8; - } else { - current_sp += ctx.free_stack_slots.back(); - ctx.free_stack_slots.pop_back(); - } + inst_stack_space += 8; switch (GetRegBytesOfType(IR::Value(inst))) { case 1: return byte[r11 + current_sp]; @@ -192,14 +187,12 @@ void EmitContext::SpillInst(RegAllocContext& ctx, const ActiveInstInterval& inte [](const ActiveInstInterval& a, const ActiveInstInterval& b) { return a.end < b.end; }); if (spill_candidate == active_intervals.end() || spill_candidate->end <= interval.start) { inst_to_operands[interval.inst][interval.component] = get_operand(interval.inst); - ctx.active_spill_intervals.push_back(interval); } else { Operands& operands = inst_to_operands[spill_candidate->inst]; - Reg reg = operands[spill_candidate->component].Reg(); + OperandHolder op = operands[spill_candidate->component]; inst_to_operands[interval.inst][interval.component] = - reg.isXMM() ? reg : ResizeRegToType(reg, interval.inst); + op.IsXmm() ? op : ResizeRegToType(op.Reg(), interval.inst); operands[spill_candidate->component] = get_operand(spill_candidate->inst); - ctx.active_spill_intervals.push_back(*spill_candidate); *spill_candidate = interval; } } @@ -304,16 +297,6 @@ void EmitContext::AllocateRegisters() { ++it; } } - for (auto it = ctx.active_spill_intervals.begin(); - it != ctx.active_spill_intervals.end();) { - if (it->end < interval.start) { - const Address& addr = inst_to_operands[it->inst][it->component].Mem(); - ctx.free_stack_slots.push_back(addr.getDisp()); - it = ctx.active_spill_intervals.erase(it); - } else { - ++it; - } - } u8 num_components = GetNumComponentsOfType(interval.inst); bool is_floating = IsFloatingType(interval.inst); auto& operands = inst_to_operands[interval.inst]; diff --git a/src/shader_recompiler/backend/asm_x64/x64_emit_context.h b/src/shader_recompiler/backend/asm_x64/x64_emit_context.h index ce9921233..ad0e1da6d 100644 --- a/src/shader_recompiler/backend/asm_x64/x64_emit_context.h +++ b/src/shader_recompiler/backend/asm_x64/x64_emit_context.h @@ -154,10 +154,8 @@ private: struct RegAllocContext { boost::container::static_vector free_gp_regs; boost::container::static_vector free_xmm_regs; - boost::container::small_vector free_stack_slots; ActiveIntervalList active_gp_intervals; ActiveIntervalList active_xmm_intervals; - ActiveIntervalList active_spill_intervals; }; using FlatInstList = boost::container::small_vector;