tile: Do not pad mip height to tile height.

This commit is contained in:
squidbus 2025-01-21 20:57:45 -08:00
parent bc344e4a52
commit b1e3547ccc

View File

@ -178,7 +178,6 @@ void ImageInfo::UpdateSize() {
case AmdGpu::TilingMode::Display_Linear: { case AmdGpu::TilingMode::Display_Linear: {
std::tie(mip_info.pitch, mip_info.size) = std::tie(mip_info.pitch, mip_info.size) =
ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples); ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
mip_info.height = mip_h;
break; break;
} }
case AmdGpu::TilingMode::Texture_Volume: case AmdGpu::TilingMode::Texture_Volume:
@ -189,11 +188,6 @@ void ImageInfo::UpdateSize() {
case AmdGpu::TilingMode::Texture_MicroTiled: { case AmdGpu::TilingMode::Texture_MicroTiled: {
std::tie(mip_info.pitch, mip_info.size) = std::tie(mip_info.pitch, mip_info.size) =
ImageSizeMicroTiled(mip_w, mip_h, thickness, bpp, num_samples); ImageSizeMicroTiled(mip_w, mip_h, thickness, bpp, num_samples);
mip_info.height = std::max(mip_h, 8u);
if (props.is_block) {
mip_info.pitch = std::max(mip_info.pitch * 4, 32u);
mip_info.height = std::max(mip_info.height * 4, 32u);
}
break; break;
} }
case AmdGpu::TilingMode::Display_MacroTiled: case AmdGpu::TilingMode::Display_MacroTiled:
@ -208,6 +202,11 @@ void ImageInfo::UpdateSize() {
UNREACHABLE(); UNREACHABLE();
} }
} }
mip_info.height = mip_h;
if (props.is_block) {
mip_info.pitch = std::max(mip_info.pitch * 4, 32u);
mip_info.height = std::max(mip_info.height * 4, 32u);
}
mip_info.size *= mip_d; mip_info.size *= mip_d;
mip_info.offset = guest_size; mip_info.offset = guest_size;
mips_layout.emplace_back(mip_info); mips_layout.emplace_back(mip_info);