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https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
more cleanup
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3c5dbe567c
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@ -510,7 +510,6 @@ void EmitContext::DefineOutputs() {
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break;
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}
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case LogicalStage::TessellationEval: {
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// TODO copied from logical vertex, figure this out
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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const bool has_extra_pos_stores = info.stores.Get(IR::Attribute::Position1) ||
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info.stores.Get(IR::Attribute::Position2) ||
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@ -129,7 +129,7 @@ void Translator::EmitPrologue() {
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// [8:12]: output control point id
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ir.SetVectorReg(IR::VectorReg::V1,
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ir.GetAttributeU32(IR::Attribute::PackedHullInvocationInfo));
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// TODO need PrimitiveId also like TES? Havent seen it yet but probably V2
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// TODO PrimitiveId is probably V2 but haven't seen it yet
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break;
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}
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case LogicalStage::TessellationEval:
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@ -175,7 +175,6 @@ struct Info {
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PersistentSrtInfo srt_info;
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std::vector<u32> flattened_ud_buf;
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// TODO handle indirection
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IR::ScalarReg tess_consts_ptr_base = IR::ScalarReg::Max;
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s32 tess_consts_dword_offset = -1;
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@ -293,14 +293,6 @@ void FoldReadLane(IR::Block& block, IR::Inst& inst) {
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}
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}
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void FoldTessAttrAccess(IR::Inst& inst) {
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if (inst.GetOpcode() == IR::Opcode::GetTessGenericAttribute) {
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// Fold the vertex index
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}
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// Fold the attr index
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// Fold the component index
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}
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void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::IAdd32:
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@ -481,9 +473,6 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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return FoldConvert(inst, IR::Opcode::ConvertF16F32);
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case IR::Opcode::ConvertF16F32:
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return FoldConvert(inst, IR::Opcode::ConvertF32F16);
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case IR::Opcode::GetTessGenericAttribute:
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case IR::Opcode::SetTcsGenericAttribute:
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return FoldTessAttrAccess(inst);
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default:
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break;
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}
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@ -104,7 +104,7 @@ inline auto MakeInstPattern(Args&&... args) {
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return MatchInstObject<opcode, Args...>(std::forward<Args>(args)...);
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}
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// Conveniences. TODO maybe delete
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// Conveniences. TODO probably simpler way of doing this
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#define M_READCONST(...) MakeInstPattern<IR::Opcode::ReadConst>(__VA_ARGS__)
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#define M_GETUSERDATA(...) MakeInstPattern<IR::Opcode::GetUserData>(__VA_ARGS__)
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#define M_BITFIELDUEXTRACT(...) MakeInstPattern<IR::Opcode::BitFieldUExtract>(__VA_ARGS__)
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@ -49,10 +49,6 @@ void Rasterizer::CpSync() {
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bool Rasterizer::FilterDraw() {
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const auto& regs = liverpool->regs;
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// Tessellation is unsupported so skip the draw to avoid locking up the driver.
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// if (regs.primitive_type == AmdGpu::PrimitiveType::PatchPrimitive) {
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// return false;
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// }
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// There are several cases (e.g. FCE, FMask/HTile decompression) where we don't need to do an
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// actual draw hence can skip pipeline creation.
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if (regs.color_control.mode == Liverpool::ColorControl::OperationMode::EliminateFastClear) {
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