mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-08-04 16:32:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

more cleanup

Browse Source
This commit is contained in:
Frodo Baggins 2024-12-14 00:37:22 -08:00
parent 3c5dbe567c
commit b9148aa811
6 changed files with 2 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/shader_recompiler/backend/spirv/spirv_emit_context.cpp
View File

@ -510,7 +510,6 @@ void EmitContext::DefineOutputs() {
break; break;
} }
case LogicalStage::TessellationEval: { case LogicalStage::TessellationEval: {
// TODO copied from logical vertex, figure this out
output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output); output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
const bool has_extra_pos_stores = info.stores.Get(IR::Attribute::Position1) || const bool has_extra_pos_stores = info.stores.Get(IR::Attribute::Position1) ||
info.stores.Get(IR::Attribute::Position2) || info.stores.Get(IR::Attribute::Position2) ||

2
src/shader_recompiler/frontend/translate/translate.cpp
View File

@ -129,7 +129,7 @@ void Translator::EmitPrologue() {
// [8:12]: output control point id // [8:12]: output control point id
ir.SetVectorReg(IR::VectorReg::V1, ir.SetVectorReg(IR::VectorReg::V1,
ir.GetAttributeU32(IR::Attribute::PackedHullInvocationInfo)); ir.GetAttributeU32(IR::Attribute::PackedHullInvocationInfo));
// TODO need PrimitiveId also like TES? Havent seen it yet but probably V2 // TODO PrimitiveId is probably V2 but haven't seen it yet
break; break;
} }
case LogicalStage::TessellationEval: case LogicalStage::TessellationEval:

1
src/shader_recompiler/info.h
View File

@ -175,7 +175,6 @@ struct Info {
PersistentSrtInfo srt_info; PersistentSrtInfo srt_info;
std::vector<u32> flattened_ud_buf; std::vector<u32> flattened_ud_buf;
// TODO handle indirection
IR::ScalarReg tess_consts_ptr_base = IR::ScalarReg::Max; IR::ScalarReg tess_consts_ptr_base = IR::ScalarReg::Max;
s32 tess_consts_dword_offset = -1; s32 tess_consts_dword_offset = -1;

11
src/shader_recompiler/ir/passes/constant_propagation_pass.cpp
View File

@ -293,14 +293,6 @@ void FoldReadLane(IR::Block& block, IR::Inst& inst) {
} }
} }
void FoldTessAttrAccess(IR::Inst& inst) {
if (inst.GetOpcode() == IR::Opcode::GetTessGenericAttribute) {
// Fold the vertex index
}
// Fold the attr index
// Fold the component index
}
void ConstantPropagation(IR::Block& block, IR::Inst& inst) { void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
switch (inst.GetOpcode()) { switch (inst.GetOpcode()) {
case IR::Opcode::IAdd32: case IR::Opcode::IAdd32:
@ -481,9 +473,6 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
return FoldConvert(inst, IR::Opcode::ConvertF16F32); return FoldConvert(inst, IR::Opcode::ConvertF16F32);
case IR::Opcode::ConvertF16F32: case IR::Opcode::ConvertF16F32:
return FoldConvert(inst, IR::Opcode::ConvertF32F16); return FoldConvert(inst, IR::Opcode::ConvertF32F16);
case IR::Opcode::GetTessGenericAttribute:
case IR::Opcode::SetTcsGenericAttribute:
return FoldTessAttrAccess(inst);
default: default:
break; break;
} }

2
src/shader_recompiler/ir/pattern_matching.h
View File

@ -104,7 +104,7 @@ inline auto MakeInstPattern(Args&&... args) {
return MatchInstObject<opcode, Args...>(std::forward<Args>(args)...); return MatchInstObject<opcode, Args...>(std::forward<Args>(args)...);
} }
// Conveniences. TODO maybe delete // Conveniences. TODO probably simpler way of doing this
#define M_READCONST(...) MakeInstPattern<IR::Opcode::ReadConst>(__VA_ARGS__) #define M_READCONST(...) MakeInstPattern<IR::Opcode::ReadConst>(__VA_ARGS__)
#define M_GETUSERDATA(...) MakeInstPattern<IR::Opcode::GetUserData>(__VA_ARGS__) #define M_GETUSERDATA(...) MakeInstPattern<IR::Opcode::GetUserData>(__VA_ARGS__)
#define M_BITFIELDUEXTRACT(...) MakeInstPattern<IR::Opcode::BitFieldUExtract>(__VA_ARGS__) #define M_BITFIELDUEXTRACT(...) MakeInstPattern<IR::Opcode::BitFieldUExtract>(__VA_ARGS__)

4
src/video_core/renderer_vulkan/vk_rasterizer.cpp
View File

@ -49,10 +49,6 @@ void Rasterizer::CpSync() {
bool Rasterizer::FilterDraw() { bool Rasterizer::FilterDraw() {
const auto& regs = liverpool->regs; const auto& regs = liverpool->regs;
// Tessellation is unsupported so skip the draw to avoid locking up the driver.
// if (regs.primitive_type == AmdGpu::PrimitiveType::PatchPrimitive) {
// return false;
// }
// There are several cases (e.g. FCE, FMask/HTile decompression) where we don't need to do an // There are several cases (e.g. FCE, FMask/HTile decompression) where we don't need to do an
// actual draw hence can skip pipeline creation. // actual draw hence can skip pipeline creation.
if (regs.color_control.mode == Liverpool::ColorControl::OperationMode::EliminateFastClear) { if (regs.color_control.mode == Liverpool::ColorControl::OperationMode::EliminateFastClear) {