From c73aff3f8d74f1d3a064120de80ea41d66402509 Mon Sep 17 00:00:00 2001
From: Vinicius Rangel <me@viniciusrangel.dev>
Date: Tue, 23 Jul 2024 15:52:01 -0300
Subject: [PATCH] fix V_ADDC_U32 carry

---
 src/shader_recompiler/frontend/translate/vector_alu.cpp | 9 +++++----
 src/shader_recompiler/ir/ir_emitter.cpp                 | 1 +
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
index 650b8907c..56101db64 100644
--- a/src/shader_recompiler/frontend/translate/vector_alu.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -97,14 +97,15 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
     const auto src0 = GetSrc<IR::U32>(inst.src[0]);
     const auto src1 = GetSrc<IR::U32>(inst.src[1]);
 
-    IR::U32 scarry;
+    IR::U1 scarry;
     if (inst.src_count == 3) { // VOP3
-        scarry = GetSrc<IR::U32>(inst.src[2]);
+        scarry = ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[2].code));
     } else { // VOP2
-        scarry = ir.GetVccLo();
+        scarry = ir.GetVcc();
     }
 
-    IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), scarry);
+    const IR::U32 carry_v{ir.Select(scarry, ir.Imm32(1), ir.Imm32(0))};
+    IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), carry_v);
 
     const IR::VectorReg dst_reg{inst.dst[0].code};
     ir.SetVectorReg(dst_reg, result);
diff --git a/src/shader_recompiler/ir/ir_emitter.cpp b/src/shader_recompiler/ir/ir_emitter.cpp
index 6df407e88..5cc96c800 100644
--- a/src/shader_recompiler/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/ir/ir_emitter.cpp
@@ -243,6 +243,7 @@ U1 IREmitter::GetExec() {
 }
 
 U1 IREmitter::GetVcc() {
+    // FIXME Should it be a thread bit?
     return Inst<U1>(Opcode::GetVcc);
 }