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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: added support for fetch instance id
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@ -72,6 +72,9 @@ std::vector<VertexAttribute> ParseFetchShader(const u32* code) {
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attrib.sgpr_base = it->base_sgpr;
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attrib.sgpr_base = it->base_sgpr;
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attrib.dword_offset = it->dword_offset;
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attrib.dword_offset = it->dword_offset;
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// Store instance id rate
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attrib.instance_data = inst.src[0].code;
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// Mark load as used.
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// Mark load as used.
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it->dst_reg = -1;
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it->dst_reg = -1;
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}
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}
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@ -9,11 +9,12 @@
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namespace Shader::Gcn {
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namespace Shader::Gcn {
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struct VertexAttribute {
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struct VertexAttribute {
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u8 semantic; ///< Semantic index of the attribute
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u8 semantic; ///< Semantic index of the attribute
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u8 dest_vgpr; ///< Destination VGPR to load first component.
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u8 dest_vgpr; ///< Destination VGPR to load first component.
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u8 num_elements; ///< Number of components to load
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u8 num_elements; ///< Number of components to load
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u8 sgpr_base; ///< SGPR that contains the pointer to the list of vertex V#
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u8 sgpr_base; ///< SGPR that contains the pointer to the list of vertex V#
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u8 dword_offset; ///< The dword offset of the V# that describes this attribute.
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u8 dword_offset; ///< The dword offset of the V# that describes this attribute.
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u8 instance_data; ///< Indicates that the buffer will be accessed in instance rate
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};
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};
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std::vector<VertexAttribute> ParseFetchShader(const u32* code);
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std::vector<VertexAttribute> ParseFetchShader(const u32* code);
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@ -194,6 +194,11 @@ void Translator::EmitFetch(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg++, ir.GetAttribute(attr, i));
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ir.SetVectorReg(dst_reg++, ir.GetAttribute(attr, i));
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}
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}
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if (attrib.instance_data == 2 || attrib.instance_data == 3) {
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LOG_WARNING(Render_Recompiler, "Unsupported instance step rate = {}",
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attrib.instance_data);
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}
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// Read the V# of the attribute to figure out component number and type.
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// Read the V# of the attribute to figure out component number and type.
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const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
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const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
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const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
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const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
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@ -203,6 +208,7 @@ void Translator::EmitFetch(const GcnInst& inst) {
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.num_components = std::min<u16>(attrib.num_elements, num_components),
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.num_components = std::min<u16>(attrib.num_elements, num_components),
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.sgpr_base = attrib.sgpr_base,
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.sgpr_base = attrib.sgpr_base,
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.dword_offset = attrib.dword_offset,
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.dword_offset = attrib.dword_offset,
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.instance_step_rate = static_cast<Info::VsInput::InstanceIdType>(attrib.instance_data),
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});
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});
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}
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}
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}
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}
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@ -72,11 +72,19 @@ using SamplerResourceList = boost::container::static_vector<SamplerResource, 8>;
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struct Info {
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struct Info {
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struct VsInput {
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struct VsInput {
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enum InstanceIdType : u8 {
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None = 0,
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OverStepRate0 = 1,
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OverStepRate1 = 2,
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Plain = 3,
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};
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AmdGpu::NumberFormat fmt;
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AmdGpu::NumberFormat fmt;
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u16 binding;
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u16 binding;
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u16 num_components;
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u16 num_components;
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u8 sgpr_base;
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u8 sgpr_base;
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u8 dword_offset;
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u8 dword_offset;
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InstanceIdType instance_step_rate;
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};
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};
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boost::container::static_vector<VsInput, 32> vs_inputs{};
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boost::container::static_vector<VsInput, 32> vs_inputs{};
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@ -53,7 +53,9 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
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bindings.push_back({
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bindings.push_back({
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.binding = input.binding,
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.binding = input.binding,
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.stride = buffer.GetStride(),
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.stride = buffer.GetStride(),
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.inputRate = vk::VertexInputRate::eVertex,
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.inputRate = input.instance_step_rate == Shader::Info::VsInput::None
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? vk::VertexInputRate::eVertex
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: vk::VertexInputRate::eInstance,
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});
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});
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}
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}
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