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Implemented V_CVT_PK_I16_I32

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Implemented this opcode to help with https://github.com/shadps4-emu/shadps4-game-compatibility/issues/1864
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AnthonyH26 2025-01-04 12:52:03 +00:00 committed by GitHub
parent 0de2f642b8
commit cf9f3daa74
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1 changed files with 13 additions and 0 deletions
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13
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -375,6 +375,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_SAD_U32(inst); return V_SAD_U32(inst);
case Opcode::V_CVT_PK_U16_U32: case Opcode::V_CVT_PK_U16_U32:
return V_CVT_PK_U16_U32(inst); return V_CVT_PK_U16_U32(inst);
case Opcode::V_CVT_PK_I16_I32:
return V_CVT_PK_I16_I32(inst);
case Opcode::V_CVT_PK_U8_F32: case Opcode::V_CVT_PK_U8_F32:
return V_CVT_PK_U8_F32(inst); return V_CVT_PK_U8_F32(inst);
case Opcode::V_LSHL_B64: case Opcode::V_LSHL_B64:
@ -1182,6 +1184,17 @@ void Translator::V_CVT_PK_U16_U32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.BitFieldInsert(lo, hi, ir.Imm32(16), ir.Imm32(16))); SetDst(inst.dst[0], ir.BitFieldInsert(lo, hi, ir.Imm32(16), ir.Imm32(16)));
} }
void Translator::V_CVT_PK_I16_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
//Clamp the underflow then clamp the overflow from the result
IR::U32 lo = ir.IMax(src0, ir.Imm32(0x8000), true);
lo = ir.IMin(lo, ir.Imm32(0x7FFF), true);
IR::U32 hi = ir.IMax(src1, ir.Imm32(0x8000), true);
hi = ir.IMin(hi, ir.Imm32(0x7FFF), true);
SetDst(inst.dst[0], ir.BitFieldInsert(lo, hi, ir.Imm32(16), ir.Imm32(16)));
}
void Translator::V_CVT_PK_U8_F32(const GcnInst& inst) { void Translator::V_CVT_PK_U8_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])}; const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])}; const IR::U32 src1{GetSrc(inst.src[1])};