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https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-05 08:52:36 +00:00
renderer_vulkan: Use tessellation for quad primitive as well
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0925d58924
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cff8124943
@ -130,21 +130,37 @@ struct QuadRectListEmitter : public Sirit::Module {
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}
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/// Emits a passthrough quad tessellation control shader that outputs 4 control points.
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void EmitPassthroughTCS() {
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void EmitQuadListTCS() {
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DefineEntry(spv::ExecutionModel::TessellationControl);
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const Id array_type{TypeArray(int_id, Int(4))};
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const Id values{ConstantComposite(array_type, Int(1), Int(2), Int(0), Int(3))};
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const Id indices{AddLocalVariable(TypePointer(spv::StorageClass::Function, array_type),
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spv::StorageClass::Function, values)};
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// Set passthrough tessellation factors
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const Id output_float{TypePointer(spv::StorageClass::Output, float_id)};
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for (int i = 0; i < 4; i++) {
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const Id ptr{OpAccessChain(output_float, gl_tess_level_outer, Int(i))};
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OpStore(ptr, float_one);
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}
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for (int i = 0; i < 2; i++) {
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const Id ptr{OpAccessChain(output_float, gl_tess_level_inner, Int(i))};
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OpStore(ptr, float_one);
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}
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const Id input_vec4{TypePointer(spv::StorageClass::Input, vec4_id)};
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const Id output_vec4{TypePointer(spv::StorageClass::Output, vec4_id)};
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const Id func_int{TypePointer(spv::StorageClass::Function, int_id)};
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const Id invocation_id{OpLoad(int_id, gl_invocation_id)};
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const Id index{OpLoad(int_id, OpAccessChain(func_int, indices, invocation_id))};
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// gl_out[gl_InvocationID].gl_Position = gl_in[gl_InvocationID].gl_Position;
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const Id in_position{
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OpLoad(vec4_id, OpAccessChain(input_vec4, gl_in, invocation_id, Int(0)))};
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const Id in_position{OpLoad(vec4_id, OpAccessChain(input_vec4, gl_in, index, Int(0)))};
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OpStore(OpAccessChain(output_vec4, gl_out, invocation_id, Int(0)), in_position);
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for (int i = 0; i < num_attribs; i++) {
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// out_paramN[gl_InvocationID] = in_paramN[gl_InvocationID];
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const Id in_param{OpLoad(vec4_id, OpAccessChain(input_vec4, inputs[i], invocation_id))};
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const Id in_param{OpLoad(vec4_id, OpAccessChain(input_vec4, inputs[i], index))};
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OpStore(OpAccessChain(output_vec4, outputs[i], invocation_id), in_param);
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}
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@ -296,8 +312,8 @@ std::vector<u32> EmitAuxilaryTessShader(AuxShaderType type, size_t num_attribs)
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case AuxShaderType::RectListTCS:
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ctx.EmitRectListTCS();
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break;
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case AuxShaderType::PassthoughTCS:
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ctx.EmitPassthroughTCS();
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case AuxShaderType::QuadListTCS:
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ctx.EmitQuadListTCS();
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break;
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case AuxShaderType::PassthroughTES:
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ctx.EmitPassthroughTES();
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@ -10,7 +10,7 @@ namespace Shader::Backend::SPIRV {
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enum class AuxShaderType : u32 {
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RectListTCS,
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PassthoughTCS,
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QuadListTCS,
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PassthroughTES,
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};
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@ -238,32 +238,14 @@ u32 BufferCache::BindIndexBuffer(bool& is_indexed, u32 index_offset) {
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// Emulate QuadList and Polygon primitive types with CPU made index buffer.
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const auto& regs = liverpool->regs;
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if (!is_indexed) {
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bool needs_index_buffer = false;
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if (regs.primitive_type == AmdGpu::PrimitiveType::QuadList ||
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regs.primitive_type == AmdGpu::PrimitiveType::Polygon) {
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needs_index_buffer = true;
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}
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if (!needs_index_buffer) {
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if (regs.primitive_type != AmdGpu::PrimitiveType::Polygon) {
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return regs.num_indices;
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}
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// Emit indices.
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const u32 index_size = 3 * regs.num_indices;
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const auto [data, offset] = stream_buffer.Map(index_size);
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switch (regs.primitive_type) {
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case AmdGpu::PrimitiveType::QuadList:
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Vulkan::LiverpoolToVK::EmitQuadToTriangleListIndices(data, regs.num_indices);
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break;
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case AmdGpu::PrimitiveType::Polygon:
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Vulkan::LiverpoolToVK::EmitPolygonToTriangleListIndices(data, regs.num_indices);
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break;
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default:
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UNREACHABLE();
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break;
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}
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Vulkan::LiverpoolToVK::EmitPolygonToTriangleListIndices(data, regs.num_indices);
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stream_buffer.Commit();
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// Bind index buffer.
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@ -282,31 +264,6 @@ u32 BufferCache::BindIndexBuffer(bool& is_indexed, u32 index_offset) {
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VAddr index_address = regs.index_base_address.Address<VAddr>();
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index_address += index_offset * index_size;
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if (regs.primitive_type == AmdGpu::PrimitiveType::QuadList) {
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// Convert indices.
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const u32 new_index_size = regs.num_indices * index_size * 6 / 4;
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const auto [data, offset] = stream_buffer.Map(new_index_size);
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const auto index_ptr = reinterpret_cast<u8*>(index_address);
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switch (index_type) {
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case vk::IndexType::eUint16:
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Vulkan::LiverpoolToVK::ConvertQuadToTriangleListIndices<u16>(data, index_ptr,
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regs.num_indices);
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break;
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case vk::IndexType::eUint32:
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Vulkan::LiverpoolToVK::ConvertQuadToTriangleListIndices<u32>(data, index_ptr,
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regs.num_indices);
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break;
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default:
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UNREACHABLE_MSG("Unsupported QuadList index type {}", vk::to_string(index_type));
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break;
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}
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stream_buffer.Commit();
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// Bind index buffer.
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const auto cmdbuf = scheduler.CommandBuffer();
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cmdbuf.bindIndexBuffer(stream_buffer.Handle(), offset, index_type);
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return new_index_size / index_size;
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}
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if (regs.primitive_type == AmdGpu::PrimitiveType::Polygon) {
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UNREACHABLE();
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}
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@ -116,10 +116,10 @@ vk::PrimitiveTopology PrimitiveType(AmdGpu::PrimitiveType type) {
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return vk::PrimitiveTopology::eTriangleStripWithAdjacency;
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case AmdGpu::PrimitiveType::PatchPrimitive:
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return vk::PrimitiveTopology::ePatchList;
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case AmdGpu::PrimitiveType::QuadList:
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case AmdGpu::PrimitiveType::Polygon:
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// Needs to generate index buffer on the fly.
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return vk::PrimitiveTopology::eTriangleList;
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case AmdGpu::PrimitiveType::QuadList:
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case AmdGpu::PrimitiveType::RectList:
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return vk::PrimitiveTopology::ePatchList;
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default:
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@ -70,34 +70,6 @@ vk::ClearValue ColorBufferClearValue(const AmdGpu::Liverpool::ColorBuffer& color
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vk::SampleCountFlagBits NumSamples(u32 num_samples, vk::SampleCountFlags supported_flags);
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static constexpr u16 NumVerticesPerQuad = 4;
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inline void EmitQuadToTriangleListIndices(u8* out_ptr, u32 num_vertices) {
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u16* out_data = reinterpret_cast<u16*>(out_ptr);
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for (u16 i = 0; i < num_vertices; i += NumVerticesPerQuad) {
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*out_data++ = i;
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*out_data++ = i + 1;
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*out_data++ = i + 2;
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*out_data++ = i;
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*out_data++ = i + 2;
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*out_data++ = i + 3;
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}
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}
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template <typename T>
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void ConvertQuadToTriangleListIndices(u8* out_ptr, const u8* in_ptr, u32 num_vertices) {
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T* out_data = reinterpret_cast<T*>(out_ptr);
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const T* in_data = reinterpret_cast<const T*>(in_ptr);
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for (u16 i = 0; i < num_vertices; i += NumVerticesPerQuad) {
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*out_data++ = in_data[i];
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*out_data++ = in_data[i + 1];
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*out_data++ = in_data[i + 2];
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*out_data++ = in_data[i];
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*out_data++ = in_data[i + 2];
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*out_data++ = in_data[i + 3];
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}
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}
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inline void EmitPolygonToTriangleListIndices(u8* out_ptr, u32 num_vertices) {
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u16* out_data = reinterpret_cast<u16*>(out_ptr);
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for (u16 i = 1; i < num_vertices - 1; i++) {
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@ -107,10 +107,11 @@ GraphicsPipeline::GraphicsPipeline(
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key.primitive_restart_index == 0xFFFFFFFF,
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"Primitive restart index other than -1 is not supported yet");
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const bool is_rect_list = key.prim_type == AmdGpu::PrimitiveType::RectList;
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const bool is_quad_list = key.prim_type == AmdGpu::PrimitiveType::QuadList;
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const size_t num_fs_inputs =
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runtime_infos[u32(Shader::LogicalStage::Fragment)].fs_info.num_inputs;
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const vk::PipelineTessellationStateCreateInfo tessellation_state = {
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.patchControlPoints = is_rect_list ? 3U : key.patch_control_points,
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.patchControlPoints = is_rect_list ? 3U : (is_quad_list ? 4U : key.patch_control_points),
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};
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const vk::PipelineRasterizationStateCreateInfo raster_state = {
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@ -234,9 +235,9 @@ GraphicsPipeline::GraphicsPipeline(
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.module = modules[stage],
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.pName = "main",
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});
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} else if (is_rect_list) {
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auto tcs = Shader::Backend::SPIRV::EmitAuxilaryTessShader(AuxShaderType::RectListTCS,
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num_fs_inputs);
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} else if (is_rect_list || is_quad_list) {
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const auto type = is_quad_list ? AuxShaderType::QuadListTCS : AuxShaderType::RectListTCS;
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auto tcs = Shader::Backend::SPIRV::EmitAuxilaryTessShader(type, num_fs_inputs);
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shader_stages.emplace_back(vk::PipelineShaderStageCreateInfo{
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.stage = vk::ShaderStageFlagBits::eTessellationControl,
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.module = CompileSPV(tcs, instance.GetDevice()),
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@ -250,7 +251,7 @@ GraphicsPipeline::GraphicsPipeline(
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.module = modules[stage],
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.pName = "main",
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});
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} else if (is_rect_list) {
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} else if (is_rect_list || is_quad_list) {
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auto tes = Shader::Backend::SPIRV::EmitAuxilaryTessShader(AuxShaderType::PassthroughTES,
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num_fs_inputs);
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shader_stages.emplace_back(vk::PipelineShaderStageCreateInfo{
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@ -18,7 +18,7 @@ class TextureCache;
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namespace Vulkan {
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static constexpr u32 MaxShaderStages = 5;
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static constexpr u32 MaxShaderStages = static_cast<u32>(Shader::LogicalStage::NumLogicalStages);
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static constexpr u32 MaxVertexBufferCount = 32;
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class Instance;
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@ -237,9 +237,7 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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cmdbuf.drawIndexed(num_indices, regs.num_instances.NumInstances(), 0, s32(vertex_offset),
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instance_offset);
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} else {
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const u32 num_vertices =
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regs.primitive_type == AmdGpu::PrimitiveType::RectList ? 3 : regs.num_indices;
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cmdbuf.draw(num_vertices, regs.num_instances.NumInstances(), vertex_offset,
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cmdbuf.draw(num_indices, regs.num_instances.NumInstances(), vertex_offset,
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instance_offset);
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}
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@ -255,18 +253,14 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u3
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}
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const auto& regs = liverpool->regs;
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if (regs.primitive_type == AmdGpu::PrimitiveType::QuadList ||
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regs.primitive_type == AmdGpu::PrimitiveType::Polygon) {
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// We use a generated index buffer to convert quad lists and polygons to triangles. Since it
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if (regs.primitive_type == AmdGpu::PrimitiveType::Polygon) {
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// We use a generated index buffer to convert polygons to triangles. Since it
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// changes type of the draw, arguments are not valid for this case. We need to run a
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// conversion pass to repack the indirect arguments buffer first.
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LOG_WARNING(Render_Vulkan, "Primitive type is not supported for indirect draw");
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return;
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}
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ASSERT_MSG(regs.primitive_type != AmdGpu::PrimitiveType::RectList,
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"Unsupported primitive type for indirect draw");
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const GraphicsPipeline* pipeline = pipeline_cache.GetGraphicsPipeline();
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if (!pipeline) {
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return;
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