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https://github.com/shadps4-emu/shadPS4.git
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work
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commit
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@ -2155,6 +2155,7 @@ int PS4_SYSV_ABI sceGnmSubmitCommandBuffersForWorkload() {
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int PS4_SYSV_ABI sceGnmSubmitDone() {
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int PS4_SYSV_ABI sceGnmSubmitDone() {
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LOG_DEBUG(Lib_GnmDriver, "called");
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LOG_DEBUG(Lib_GnmDriver, "called");
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WaitGpuIdle();
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if (!liverpool->IsGpuIdle()) {
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if (!liverpool->IsGpuIdle()) {
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submission_lock = true;
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submission_lock = true;
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}
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}
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@ -10,6 +10,7 @@
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#ifdef ENABLE_QT_GUI
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#ifdef ENABLE_QT_GUI
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#include "qt_gui/memory_patcher.h"
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#include "qt_gui/memory_patcher.h"
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#endif
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#endif
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#include "common/ntapi.h"
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#include "common/path_util.h"
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#include "common/path_util.h"
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#include "common/polyfill_thread.h"
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#include "common/polyfill_thread.h"
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#include "common/scm_rev.h"
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#include "common/scm_rev.h"
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@ -171,7 +171,7 @@ T Translator::GetSrc(const InstOperand& operand) {
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}
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}
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} else {
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} else {
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if (operand.input_modifier.abs) {
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if (operand.input_modifier.abs) {
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LOG_WARNING(Render_Vulkan, "Input abs modifier on integer instruction");
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value = ir.IAbs(value);
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}
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}
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if (operand.input_modifier.neg) {
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if (operand.input_modifier.neg) {
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UNREACHABLE();
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UNREACHABLE();
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@ -1,6 +1,5 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#pragma once
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#include <span>
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#include <span>
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@ -182,6 +181,7 @@ struct Info {
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const u32* base = user_data.data();
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const u32* base = user_data.data();
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if (ptr_index != IR::NumScalarRegs) {
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if (ptr_index != IR::NumScalarRegs) {
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std::memcpy(&base, &user_data[ptr_index], sizeof(base));
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std::memcpy(&base, &user_data[ptr_index], sizeof(base));
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base = reinterpret_cast<const u32*>(VAddr(base) & 0xFFFFFFFFFFFFULL);
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}
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}
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std::memcpy(&data, base + dword_offset, sizeof(T));
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std::memcpy(&data, base + dword_offset, sizeof(T));
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return data;
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return data;
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@ -21,8 +21,7 @@ void LowerSharedMemToRegisters(IR::Program& program) {
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const IR::Inst* prod = inst.Arg(0).InstRecursive();
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const IR::Inst* prod = inst.Arg(0).InstRecursive();
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const auto it = std::ranges::find_if(ds_writes, [&](const IR::Inst* write) {
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const auto it = std::ranges::find_if(ds_writes, [&](const IR::Inst* write) {
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const IR::Inst* write_prod = write->Arg(0).InstRecursive();
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const IR::Inst* write_prod = write->Arg(0).InstRecursive();
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return write_prod->Arg(1).U32() == prod->Arg(1).U32() &&
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return write_prod->Arg(1).U32() == prod->Arg(1).U32();
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write_prod->Arg(0) == prod->Arg(0);
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});
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});
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ASSERT(it != ds_writes.end());
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ASSERT(it != ds_writes.end());
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// Replace data read with value written.
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// Replace data read with value written.
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@ -581,9 +581,6 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb, int vqid) {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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break;
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break;
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}
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}
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case PM4ItOpcode::DmaData: {
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break;
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}
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case PM4ItOpcode::IndirectBuffer: {
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case PM4ItOpcode::IndirectBuffer: {
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const auto* indirect_buffer = reinterpret_cast<const PM4CmdIndirectBuffer*>(header);
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const auto* indirect_buffer = reinterpret_cast<const PM4CmdIndirectBuffer*>(header);
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auto task = ProcessCompute(
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auto task = ProcessCompute(
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@ -187,6 +187,11 @@ struct PM4CmdSetData {
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BitField<28, 4, u32> index; ///< Index for UCONFIG/CONTEXT on CI+
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BitField<28, 4, u32> index; ///< Index for UCONFIG/CONTEXT on CI+
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///< Program to zero for other opcodes and on SI
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///< Program to zero for other opcodes and on SI
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};
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};
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u32 data[0];
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[[nodiscard]] u32 Size() const {
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return header.count << 2u;
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}
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template <PM4ShaderType type = PM4ShaderType::ShaderGraphics, typename... Args>
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template <PM4ShaderType type = PM4ShaderType::ShaderGraphics, typename... Args>
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static constexpr u32* SetContextReg(u32* cmdbuf, Args... data) {
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static constexpr u32* SetContextReg(u32* cmdbuf, Args... data) {
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@ -350,6 +355,16 @@ struct PM4CmdEventWriteEop {
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}
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}
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};
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};
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struct PM4CmdAcquireMem {
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PM4Type3Header header;
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u32 cp_coher_cntl;
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u32 cp_coher_size_lo;
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u32 cp_coher_size_hi;
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u32 cp_coher_base_lo;
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u32 cp_coher_base_hi;
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u32 poll_interval;
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};
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enum class DmaDataDst : u32 {
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enum class DmaDataDst : u32 {
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Memory = 0,
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Memory = 0,
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Gds = 1,
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Gds = 1,
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@ -467,6 +482,10 @@ struct PM4CmdWriteData {
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};
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};
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u32 data[0];
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u32 data[0];
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u32 Size() const {
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return (header.count.Value() - 2) * 4;
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}
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template <typename T>
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template <typename T>
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void Address(T addr) {
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void Address(T addr) {
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addr64 = static_cast<u64>(addr);
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addr64 = static_cast<u64>(addr);
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@ -586,9 +586,6 @@ bool BufferCache::SynchronizeBufferFromImage(Buffer& buffer, VAddr device_addr,
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const u32 depth =
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const u32 depth =
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image.info.props.is_volume ? std::max(image.info.size.depth >> m, 1u) : 1u;
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image.info.props.is_volume ? std::max(image.info.size.depth >> m, 1u) : 1u;
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const auto& [mip_size, mip_pitch, mip_height, mip_ofs] = image.info.mips_layout[m];
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const auto& [mip_size, mip_pitch, mip_height, mip_ofs] = image.info.mips_layout[m];
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if (offset + (mip_ofs * num_layers) > buffer.SizeBytes()) {
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break;
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}
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copies.push_back({
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copies.push_back({
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.bufferOffset = offset,
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.bufferOffset = offset,
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.bufferRowLength = static_cast<u32>(mip_pitch),
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.bufferRowLength = static_cast<u32>(mip_pitch),
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@ -452,7 +452,7 @@ void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
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boost::container::static_vector<AmdGpu::Image, 32> tsharps;
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boost::container::static_vector<AmdGpu::Image, 32> tsharps;
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for (const auto& image_desc : stage->images) {
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for (const auto& image_desc : stage->images) {
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const auto tsharp = image_desc.GetSharp(*stage);
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const auto tsharp = image_desc.GetSharp(*stage);
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if (tsharp) {
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if (tsharp.GetDataFmt() != AmdGpu::DataFormat::FormatInvalid) {
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tsharps.emplace_back(tsharp);
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tsharps.emplace_back(tsharp);
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VideoCore::ImageInfo image_info{tsharp, image_desc.is_depth};
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VideoCore::ImageInfo image_info{tsharp, image_desc.is_depth};
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VideoCore::ImageViewInfo view_info{tsharp, image_desc.is_storage};
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VideoCore::ImageViewInfo view_info{tsharp, image_desc.is_storage};
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@ -184,7 +184,7 @@ const ComputePipeline* PipelineCache::GetComputePipeline() {
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}
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}
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bool ShouldSkipShader(u64 shader_hash, const char* shader_type) {
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bool ShouldSkipShader(u64 shader_hash, const char* shader_type) {
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static constexpr std::array<u64, 4> skip_hashes = {0x6f27708a, 0x6af8ef74, 0xdf795c1f, 0xc2c49a3b};
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static constexpr std::array<u64, 0> skip_hashes = {};
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if (std::ranges::contains(skip_hashes, shader_hash)) {
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if (std::ranges::contains(skip_hashes, shader_hash)) {
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LOG_WARNING(Render_Vulkan, "Skipped {} shader hash {:#x}.", shader_type, shader_hash);
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LOG_WARNING(Render_Vulkan, "Skipped {} shader hash {:#x}.", shader_type, shader_hash);
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return true;
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return true;
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@ -43,8 +43,6 @@ static VKAPI_ATTR VkBool32 VKAPI_CALL DebugUtilsCallback(
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case 0x609a13b: // Vertex attribute at location not consumed by shader
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case 0x609a13b: // Vertex attribute at location not consumed by shader
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case 0xc81ad50e:
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case 0xc81ad50e:
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case 0xb7c39078:
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case 0xb7c39078:
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case 0x30b6e267: // TODO remove this
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case 0xde55a405: // TODO remove this
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case 0x32868fde: // vkCreateBufferView(): pCreateInfo->range does not equal VK_WHOLE_SIZE
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case 0x32868fde: // vkCreateBufferView(): pCreateInfo->range does not equal VK_WHOLE_SIZE
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case 0x92d66fc1: // `pMultisampleState is NULL` for depth only passes (confirmed VL error)
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case 0x92d66fc1: // `pMultisampleState is NULL` for depth only passes (confirmed VL error)
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return VK_FALSE;
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return VK_FALSE;
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@ -151,8 +151,7 @@ vk::DescriptorSet DescriptorHeap::Commit(vk::DescriptorSetLayout set_layout) {
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// The pool has run out. Record current tick and place it in pending list.
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// The pool has run out. Record current tick and place it in pending list.
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ASSERT_MSG(result == vk::Result::eErrorOutOfPoolMemory,
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ASSERT_MSG(result == vk::Result::eErrorOutOfPoolMemory,
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"Unexpected error during descriptor set allocation {}",
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"Unexpected error during descriptor set allocation {}", vk::to_string(result));
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vk::to_string(result));
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pending_pools.emplace_back(curr_pool, master_semaphore->CurrentTick());
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pending_pools.emplace_back(curr_pool, master_semaphore->CurrentTick());
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if (const auto [pool, tick] = pending_pools.front(); master_semaphore->IsFree(tick)) {
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if (const auto [pool, tick] = pending_pools.front(); master_semaphore->IsFree(tick)) {
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curr_pool = pool;
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curr_pool = pool;
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@ -166,8 +165,7 @@ vk::DescriptorSet DescriptorHeap::Commit(vk::DescriptorSetLayout set_layout) {
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alloc_info.descriptorPool = curr_pool;
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alloc_info.descriptorPool = curr_pool;
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result = device.allocateDescriptorSets(&alloc_info, desc_sets.data());
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result = device.allocateDescriptorSets(&alloc_info, desc_sets.data());
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ASSERT_MSG(result == vk::Result::eSuccess,
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ASSERT_MSG(result == vk::Result::eSuccess,
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"Unexpected error during descriptor set allocation {}",
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"Unexpected error during descriptor set allocation {}", vk::to_string(result));
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vk::to_string(result));
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// We've changed pool so also reset descriptor batch cache.
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// We've changed pool so also reset descriptor batch cache.
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descriptor_sets.clear();
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descriptor_sets.clear();
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@ -66,6 +66,7 @@ private:
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class DescriptorHeap final {
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class DescriptorHeap final {
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static constexpr u32 DescriptorSetBatch = 32;
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static constexpr u32 DescriptorSetBatch = 32;
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public:
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public:
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explicit DescriptorHeap(const Instance& instance, MasterSemaphore* master_semaphore,
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explicit DescriptorHeap(const Instance& instance, MasterSemaphore* master_semaphore,
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std::span<const vk::DescriptorPoolSize> pool_sizes,
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std::span<const vk::DescriptorPoolSize> pool_sizes,
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@ -73,7 +73,6 @@ static vk::ImageUsageFlags ImageUsageFlags(const ImageInfo& info) {
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if (!info.IsBlockCoded() && !info.IsPacked()) {
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if (!info.IsBlockCoded() && !info.IsPacked()) {
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usage |= vk::ImageUsageFlagBits::eColorAttachment;
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usage |= vk::ImageUsageFlagBits::eColorAttachment;
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}
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}
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// In cases where an image is created as a render/depth target and cleared with compute,
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// In cases where an image is created as a render/depth target and cleared with compute,
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// we cannot predict whether it will be used as a storage image. A proper solution would
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// we cannot predict whether it will be used as a storage image. A proper solution would
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// involve re-creating the resource with a new configuration and copying previous content
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// involve re-creating the resource with a new configuration and copying previous content
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