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Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32. (#2797)

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* Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32, DS_WRITE_SRC2_B32, DS_WRITE_SRC2_B64.

* Added ir instructions for new opcodes.
Removing Write implementations.
Maping operation S_BFE_I32 as it was added in translate but wasnt pointing to anything.

* Suggestions
This commit is contained in:
Dmugetsu
2025-04-16 18:56:27 -06:00
committed by GitHub
parent 62a4182aca
commit ddc05e8a5f
7 changed files with 89 additions and 0 deletions
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src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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@@ -130,6 +130,10 @@ Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicIIncrement32(EmitContext& ctx, Id offset);
Id EmitSharedAtomicIDecrement32(EmitContext& ctx, Id offset);
Id EmitSharedAtomicISub32(EmitContext& ctx, Id offset, Id value);
Id EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2);
Id EmitCompositeConstructU32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3);
Id EmitCompositeConstructU32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4);