mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-08-03 16:02:26 +00:00
Code Issues Packages Projects Releases Wiki Activity

Stub other 64-bit loating point shader instructions

Browse Source
This commit is contained in:
Raven 2024-09-17 01:27:25 +08:00 committed by GitHub
parent 818e6e3481
commit e4231ffc46
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 40 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
src/shader_recompiler/frontend/translate/vector_alu.cpp
View File

@ -179,6 +179,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_MUL_F32(inst); return V_MUL_F32(inst);
case Opcode::V_RCP_F32: case Opcode::V_RCP_F32:
return V_RCP_F32(inst); return V_RCP_F32(inst);
case Opcode::V_RCP_F64:
return V_RCP_F64(inst);
case Opcode::V_LDEXP_F32: case Opcode::V_LDEXP_F32:
return V_LDEXP_F32(inst); return V_LDEXP_F32(inst);
case Opcode::V_FRACT_F32: case Opcode::V_FRACT_F32:
@ -196,8 +198,16 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
case Opcode::V_FMA_F32: case Opcode::V_FMA_F32:
case Opcode::V_MADAK_F32: case Opcode::V_MADAK_F32:
return V_FMA_F32(inst); return V_FMA_F32(inst);
case Opcode::V_FMA_F64:
return V_FMA_F64(inst);
case Opcode::V_MAX_F32: case Opcode::V_MAX_F32:
return V_MAX_F32(inst); return V_MAX_F32(inst);
case Opcode::V_ADD_F64:
return V_ADD_F64(inst);
case Opcode::V_MUL_F64:
return V_MUL_F64(inst);
case Opcode::V_MIN_F64:
return V_MIN_F64(inst);
case Opcode::V_MAX_F64: case Opcode::V_MAX_F64:
return V_MAX_F64(inst); return V_MAX_F64(inst);
case Opcode::V_RSQ_F32: case Opcode::V_RSQ_F32:
@ -537,6 +547,18 @@ void Translator::V_FMA_F32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPFma(src0, src1, src2)); SetDst(inst.dst[0], ir.FPFma(src0, src1, src2));
} }
void Translator::V_RCP_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc<IR::F64>(inst.src[0])};
SetDst64(inst.dst[0], ir.FPRecip(src0));
}
void Translator::V_FMA_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc<IR::F64>(inst.src[1])};
const IR::F64 src2{GetSrc<IR::F64>(inst.src[2])};
SetDst64(inst.dst[0], ir.FPFma(src0, src1, src2));
}
void Translator::V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst) { void Translator::V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])}; const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])}; const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
@ -584,6 +606,24 @@ void Translator::V_MAX_F32(const GcnInst& inst, bool is_legacy) {
SetDst(inst.dst[0], ir.FPMax(src0, src1, is_legacy)); SetDst(inst.dst[0], ir.FPMax(src0, src1, is_legacy));
} }
void Translator::V_ADD_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
SetDst64(inst.dst[0], ir.FPAdd(src0, src1));
}
void Translator::V_MUL_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
SetDst64(inst.dst[0], ir.FPMul(src0, src1));
}
void Translator::V_MIN_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
SetDst64(inst.dst[0], ir.FPMin(src0, src1));
}
void Translator::V_MAX_F64(const GcnInst& inst) { void Translator::V_MAX_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])}; const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])}; const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};