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https://github.com/shadps4-emu/shadPS4.git
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Stub other 64-bit loating point shader instructions
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parent
818e6e3481
commit
e4231ffc46
@ -179,6 +179,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_MUL_F32(inst);
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case Opcode::V_RCP_F32:
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return V_RCP_F32(inst);
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case Opcode::V_RCP_F64:
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return V_RCP_F64(inst);
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case Opcode::V_LDEXP_F32:
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return V_LDEXP_F32(inst);
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case Opcode::V_FRACT_F32:
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@ -196,8 +198,16 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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case Opcode::V_FMA_F32:
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case Opcode::V_MADAK_F32:
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return V_FMA_F32(inst);
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case Opcode::V_FMA_F64:
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return V_FMA_F64(inst);
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case Opcode::V_MAX_F32:
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return V_MAX_F32(inst);
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case Opcode::V_ADD_F64:
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return V_ADD_F64(inst);
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case Opcode::V_MUL_F64:
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return V_MUL_F64(inst);
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case Opcode::V_MIN_F64:
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return V_MIN_F64(inst);
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case Opcode::V_MAX_F64:
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return V_MAX_F64(inst);
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case Opcode::V_RSQ_F32:
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@ -537,6 +547,18 @@ void Translator::V_FMA_F32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.FPFma(src0, src1, src2));
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}
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void Translator::V_RCP_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc<IR::F64>(inst.src[0])};
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SetDst64(inst.dst[0], ir.FPRecip(src0));
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}
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void Translator::V_FMA_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc<IR::F64>(inst.src[0])};
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const IR::F64 src1{GetSrc<IR::F64>(inst.src[1])};
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const IR::F64 src2{GetSrc<IR::F64>(inst.src[2])};
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SetDst64(inst.dst[0], ir.FPFma(src0, src1, src2));
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}
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void Translator::V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst) {
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const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
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const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
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@ -584,6 +606,24 @@ void Translator::V_MAX_F32(const GcnInst& inst, bool is_legacy) {
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SetDst(inst.dst[0], ir.FPMax(src0, src1, is_legacy));
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}
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void Translator::V_ADD_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
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const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
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SetDst64(inst.dst[0], ir.FPAdd(src0, src1));
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}
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void Translator::V_MUL_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
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const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
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SetDst64(inst.dst[0], ir.FPMul(src0, src1));
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}
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void Translator::V_MIN_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
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const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
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SetDst64(inst.dst[0], ir.FPMin(src0, src1));
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}
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void Translator::V_MAX_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
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const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
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