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shader_recompiler: Implement more opcodes
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parent
2f1d2e54c6
commit
ed84d7460c
@ -92,8 +92,12 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
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break;
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case Opcode::S_BREV_B32:
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return S_BREV_B32(inst);
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case Opcode::S_BCNT1_I32_B64:
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return S_BCNT1_I32_B64(inst);
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case Opcode::S_AND_SAVEEXEC_B64:
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return S_AND_SAVEEXEC_B64(inst);
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return S_SAVEEXEC_B64(NegateMode::None, false, inst);
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case Opcode::S_ORN2_SAVEEXEC_B64:
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return S_SAVEEXEC_B64(NegateMode::Src1, true, inst);
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default:
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LogMissingOpcode(inst);
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}
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@ -540,11 +544,17 @@ void Translator::S_BREV_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.BitReverse(GetSrc(inst.src[0])));
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}
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void Translator::S_AND_SAVEEXEC_B64(const GcnInst& inst) {
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void Translator::S_BCNT1_I32_B64(const GcnInst& inst) {
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const IR::U32 result = ir.BitCount(GetSrc(inst.src[0]));
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst) {
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// This instruction normally operates on 64-bit data (EXEC, VCC, SGPRs)
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// However here we flatten it to 1-bit EXEC and 1-bit VCC. For the destination
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// SGPR we have a special IR opcode for SPGRs that act as thread masks.
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const IR::U1 exec{ir.GetExec()};
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IR::U1 exec{ir.GetExec()};
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const IR::U1 src = [&] {
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switch (inst.src[0].field) {
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case OperandField::VccLo:
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@ -568,7 +578,13 @@ void Translator::S_AND_SAVEEXEC_B64(const GcnInst& inst) {
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}
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// Update EXEC.
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const IR::U1 result = ir.LogicalAnd(exec, src);
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if (negate == NegateMode::Src1) {
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exec = ir.LogicalNot(exec);
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}
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IR::U1 result = is_or ? ir.LogicalOr(exec, src) : ir.LogicalAnd(exec, src);
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if (negate == NegateMode::Result) {
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result = ir.LogicalNot(result);
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}
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ir.SetExec(result);
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ir.SetScc(result);
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}
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@ -108,8 +108,9 @@ public:
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void S_MOV_B64(const GcnInst& inst);
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void S_NOT_B64(const GcnInst& inst);
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void S_BREV_B32(const GcnInst& inst);
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void S_BCNT1_I32_B64(const GcnInst& inst);
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void S_GETPC_B64(u32 pc, const GcnInst& inst);
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void S_AND_SAVEEXEC_B64(const GcnInst& inst);
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void S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst);
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// SOPC
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void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
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