From f1a8b7d85e4f8279f1ec59960c32dcfee0be3fb0 Mon Sep 17 00:00:00 2001 From: TheTurtle Date: Mon, 24 Nov 2025 03:26:34 +0200 Subject: [PATCH] vector_alu: Fix V_CMP_U64 (#3823) * vector_alu: Fix V_CMP_U64 * vector_alu: Also handle vcc in V_CMP_U64 --- .../frontend/translate/vector_alu.cpp | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 604efabbd..83633402c 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -1043,20 +1043,25 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const } void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) { - const IR::U64 src0{GetSrc64(inst.src[0])}; - const IR::U64 src1{GetSrc64(inst.src[1])}; + ASSERT(inst.src[1].field == OperandField::ConstZero); + const IR::U1 src0 = [&] { + switch (inst.src[0].field) { + case OperandField::ScalarGPR: + return ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)); + case OperandField::VccLo: + return ir.GetVcc(); + default: + UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field)); + } + }(); const IR::U1 result = [&] { switch (op) { case ConditionOp::EQ: - return ir.IEqual(src0, src1); + return ir.LogicalNot(src0); case ConditionOp::LG: // NE - return ir.INotEqual(src0, src1); + return src0; case ConditionOp::GT: - if (src1.IsImmediate() && src1.U64() == 0) { - ASSERT(inst.src[0].field == OperandField::ScalarGPR); - return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code))); - } - return ir.IGreaterThan(src0, src1, is_signed); + return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code))); default: UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op)); }