translate: Reimplement step rate instance id

This commit is contained in:
IndecisiveTurtle 2025-07-13 18:06:16 +03:00
parent de90601f28
commit fc3454cd9e
4 changed files with 14 additions and 11 deletions

View File

@ -92,11 +92,21 @@ void Translator::EmitPrologue(IR::Block* first_block) {
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId)); ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
// v1: instance ID, step rate 0 // v1: instance ID, step rate 0
if (runtime_info.num_input_vgprs > 0) { if (runtime_info.num_input_vgprs > 0) {
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId0)); if (runtime_info.vs_info.step_rate_0 != 0) {
ir.SetVectorReg(dst_vreg++, ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
ir.Imm32(runtime_info.vs_info.step_rate_0)));
} else {
ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
}
} }
// v2: instance ID, step rate 1 // v2: instance ID, step rate 1
if (runtime_info.num_input_vgprs > 1) { if (runtime_info.num_input_vgprs > 1) {
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId1)); if (runtime_info.vs_info.step_rate_1 != 0) {
ir.SetVectorReg(dst_vreg++, ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
ir.Imm32(runtime_info.vs_info.step_rate_1)));
} else {
ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
}
} }
// v3: instance ID, plain // v3: instance ID, plain
if (runtime_info.num_input_vgprs > 2) { if (runtime_info.num_input_vgprs > 2) {
@ -183,10 +193,8 @@ void Translator::EmitPrologue(IR::Block* first_block) {
switch (runtime_info.gs_info.out_primitive[0]) { switch (runtime_info.gs_info.out_primitive[0]) {
case AmdGpu::GsOutputPrimitiveType::TriangleStrip: case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
ir.SetVectorReg(IR::VectorReg::V3, ir.Imm32(2u)); // vertex 2 ir.SetVectorReg(IR::VectorReg::V3, ir.Imm32(2u)); // vertex 2
[[fallthrough]];
case AmdGpu::GsOutputPrimitiveType::LineStrip: case AmdGpu::GsOutputPrimitiveType::LineStrip:
ir.SetVectorReg(IR::VectorReg::V1, ir.Imm32(1u)); // vertex 1 ir.SetVectorReg(IR::VectorReg::V1, ir.Imm32(1u)); // vertex 1
[[fallthrough]];
default: default:
ir.SetVectorReg(IR::VectorReg::V0, ir.Imm32(0u)); // vertex 0 ir.SetVectorReg(IR::VectorReg::V0, ir.Imm32(0u)); // vertex 0
break; break;

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@ -130,10 +130,6 @@ std::string NameOf(Attribute attribute) {
return "LocalInvocationIndex"; return "LocalInvocationIndex";
case Attribute::FragCoord: case Attribute::FragCoord:
return "FragCoord"; return "FragCoord";
case Attribute::InstanceId0:
return "InstanceId0";
case Attribute::InstanceId1:
return "InstanceId1";
case Attribute::InvocationId: case Attribute::InvocationId:
return "InvocationId"; return "InvocationId";
case Attribute::PatchVertices: case Attribute::PatchVertices:

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@ -73,8 +73,6 @@ enum class Attribute : u64 {
LocalInvocationId = 76, LocalInvocationId = 76,
LocalInvocationIndex = 77, LocalInvocationIndex = 77,
FragCoord = 78, FragCoord = 78,
InstanceId0 = 79, // step rate 0
InstanceId1 = 80, // step rate 1
InvocationId = 81, // TCS id in output patch and instanced geometry shader id InvocationId = 81, // TCS id in output patch and instanced geometry shader id
PatchVertices = 82, PatchVertices = 82,
TessellationEvaluationPointU = 83, TessellationEvaluationPointU = 83,

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@ -98,7 +98,8 @@ struct VertexRuntimeInfo {
clip_disable == other.clip_disable && tess_type == other.tess_type && clip_disable == other.clip_disable && tess_type == other.tess_type &&
tess_topology == other.tess_topology && tess_topology == other.tess_topology &&
tess_partitioning == other.tess_partitioning && tess_partitioning == other.tess_partitioning &&
hs_output_cp_stride == other.hs_output_cp_stride; hs_output_cp_stride == other.hs_output_cp_stride &&
step_rate_0 == other.step_rate_0 && step_rate_1 == other.step_rate_1;
} }
void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) { void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) {