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https://github.com/shadps4-emu/shadPS4.git
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translate: Reimplement step rate instance id
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parent
de90601f28
commit
fc3454cd9e
@ -92,11 +92,21 @@ void Translator::EmitPrologue(IR::Block* first_block) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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// v1: instance ID, step rate 0
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// v1: instance ID, step rate 0
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if (runtime_info.num_input_vgprs > 0) {
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if (runtime_info.num_input_vgprs > 0) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId0));
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if (runtime_info.vs_info.step_rate_0 != 0) {
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ir.SetVectorReg(dst_vreg++, ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
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ir.Imm32(runtime_info.vs_info.step_rate_0)));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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}
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// v2: instance ID, step rate 1
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// v2: instance ID, step rate 1
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if (runtime_info.num_input_vgprs > 1) {
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if (runtime_info.num_input_vgprs > 1) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId1));
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if (runtime_info.vs_info.step_rate_1 != 0) {
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ir.SetVectorReg(dst_vreg++, ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
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ir.Imm32(runtime_info.vs_info.step_rate_1)));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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}
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// v3: instance ID, plain
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// v3: instance ID, plain
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if (runtime_info.num_input_vgprs > 2) {
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if (runtime_info.num_input_vgprs > 2) {
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@ -183,10 +193,8 @@ void Translator::EmitPrologue(IR::Block* first_block) {
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switch (runtime_info.gs_info.out_primitive[0]) {
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switch (runtime_info.gs_info.out_primitive[0]) {
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case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
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case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
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ir.SetVectorReg(IR::VectorReg::V3, ir.Imm32(2u)); // vertex 2
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ir.SetVectorReg(IR::VectorReg::V3, ir.Imm32(2u)); // vertex 2
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[[fallthrough]];
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case AmdGpu::GsOutputPrimitiveType::LineStrip:
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case AmdGpu::GsOutputPrimitiveType::LineStrip:
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ir.SetVectorReg(IR::VectorReg::V1, ir.Imm32(1u)); // vertex 1
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ir.SetVectorReg(IR::VectorReg::V1, ir.Imm32(1u)); // vertex 1
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[[fallthrough]];
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default:
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default:
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ir.SetVectorReg(IR::VectorReg::V0, ir.Imm32(0u)); // vertex 0
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ir.SetVectorReg(IR::VectorReg::V0, ir.Imm32(0u)); // vertex 0
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break;
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break;
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@ -130,10 +130,6 @@ std::string NameOf(Attribute attribute) {
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return "LocalInvocationIndex";
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return "LocalInvocationIndex";
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case Attribute::FragCoord:
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case Attribute::FragCoord:
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return "FragCoord";
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return "FragCoord";
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case Attribute::InstanceId0:
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return "InstanceId0";
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case Attribute::InstanceId1:
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return "InstanceId1";
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case Attribute::InvocationId:
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case Attribute::InvocationId:
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return "InvocationId";
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return "InvocationId";
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case Attribute::PatchVertices:
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case Attribute::PatchVertices:
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@ -73,8 +73,6 @@ enum class Attribute : u64 {
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LocalInvocationId = 76,
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LocalInvocationId = 76,
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LocalInvocationIndex = 77,
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LocalInvocationIndex = 77,
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FragCoord = 78,
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FragCoord = 78,
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InstanceId0 = 79, // step rate 0
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InstanceId1 = 80, // step rate 1
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InvocationId = 81, // TCS id in output patch and instanced geometry shader id
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InvocationId = 81, // TCS id in output patch and instanced geometry shader id
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PatchVertices = 82,
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PatchVertices = 82,
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TessellationEvaluationPointU = 83,
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TessellationEvaluationPointU = 83,
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@ -98,7 +98,8 @@ struct VertexRuntimeInfo {
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clip_disable == other.clip_disable && tess_type == other.tess_type &&
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clip_disable == other.clip_disable && tess_type == other.tess_type &&
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tess_topology == other.tess_topology &&
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tess_topology == other.tess_topology &&
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tess_partitioning == other.tess_partitioning &&
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tess_partitioning == other.tess_partitioning &&
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hs_output_cp_stride == other.hs_output_cp_stride;
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hs_output_cp_stride == other.hs_output_cp_stride &&
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step_rate_0 == other.step_rate_0 && step_rate_1 == other.step_rate_1;
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}
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}
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void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) {
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void InitFromTessConstants(Shader::TessellationDataConstantBuffer& tess_constants) {
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