mirror of
https://github.com/shadps4-emu/shadPS4.git
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ddc05e8a5f
* Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32, DS_WRITE_SRC2_B32, DS_WRITE_SRC2_B64. * Added ir instructions for new opcodes. Removing Write implementations. Maping operation S_BFE_I32 as it was added in translate but wasnt pointing to anything. * Suggestions
232 lines
10 KiB
C++
232 lines
10 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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std::pair<Id, Id> AtomicArgs(EmitContext& ctx) {
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const Id scope{ctx.ConstU32(static_cast<u32>(spv::Scope::Device))};
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const Id semantics{ctx.u32_zero_value};
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return {scope, semantics};
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}
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Id SharedAtomicU32(EmitContext& ctx, Id offset, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const Id shift_id{ctx.ConstU32(2U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
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}
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Id SharedAtomicU32_IncDec(EmitContext& ctx, Id offset,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id)) {
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const Id shift_id{ctx.ConstU32(2U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics);
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}
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Id BufferAtomicU32BoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a conditional branch to make sure that
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// the atomic is not mistakenly executed when the index is out of bounds.
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], index, buffer_size);
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const Id ib_label = ctx.OpLabel();
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const Id oob_label = ctx.OpLabel();
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const Id end_label = ctx.OpLabel();
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ctx.OpBranchConditional(in_bounds, ib_label, oob_label);
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ctx.AddLabel(ib_label);
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const Id ib_result = emit_func();
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ctx.OpBranch(end_label);
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ctx.AddLabel(oob_label);
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const Id oob_result = ctx.u32_zero_value;
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ctx.OpBranch(end_label);
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ctx.AddLabel(end_label);
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return ctx.OpPhi(ctx.U32[1], ib_result, ib_label, oob_result, oob_label);
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}
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// Bounds checking not enabled, just perform the atomic operation.
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return emit_func();
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}
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Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const auto& buffer = ctx.buffers[handle];
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if (Sirit::ValidId(buffer.offset)) {
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address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
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}
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const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
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const auto [id, pointer_type] = buffer[EmitContext::BufferAlias::U32];
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const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index);
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return BufferAtomicU32BoundsCheck(ctx, index, buffer.size_dwords, [&] {
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return (ctx.*atomic_func)(ctx.U32[1], ptr, scope, semantics, value);
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});
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}
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Id ImageAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const auto& texture = ctx.images[handle & 0xFFFF];
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const Id pointer{ctx.OpImageTexelPointer(ctx.image_u32, texture.id, coords, ctx.ConstU32(0U))};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
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}
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} // Anonymous namespace
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Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitSharedAtomicSMax32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMax);
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}
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Id EmitSharedAtomicUMin32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMin);
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}
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Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMin);
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}
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Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicAnd);
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}
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Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicOr);
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}
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Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicXor);
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}
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Id EmitSharedAtomicISub32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicISub);
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}
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Id EmitSharedAtomicIIncrement32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32_IncDec(ctx, offset, &Sirit::Module::OpAtomicIIncrement);
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}
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Id EmitSharedAtomicIDecrement32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32_IncDec(ctx, offset, &Sirit::Module::OpAtomicIDecrement);
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}
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Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicSMin);
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}
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Id EmitBufferAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicUMin);
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}
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Id EmitBufferAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicSMax);
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}
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Id EmitBufferAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitBufferAtomicInc32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO
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UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicInc32);
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}
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Id EmitBufferAtomicDec32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO
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UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicDec32);
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}
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Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicAnd);
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}
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Id EmitBufferAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicOr);
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}
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Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicXor);
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}
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Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicExchange);
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}
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Id EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicSMin);
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}
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Id EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicUMin);
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}
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Id EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicSMax);
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}
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Id EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitImageAtomicInc32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO: This is not yet implemented
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitImageAtomicDec32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO: This is not yet implemented
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicAnd);
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}
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Id EmitImageAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicOr);
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}
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Id EmitImageAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicXor);
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}
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Id EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value) {
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return ImageAtomicU32(ctx, inst, handle, coords, value, &Sirit::Module::OpAtomicExchange);
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}
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Id EmitDataAppend(EmitContext& ctx, u32 gds_addr, u32 binding) {
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const auto& buffer = ctx.buffers[binding];
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const auto [id, pointer_type] = buffer[EmitContext::BufferAlias::U32];
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const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, ctx.ConstU32(gds_addr));
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return ctx.OpAtomicIIncrement(ctx.U32[1], ptr, scope, semantics);
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}
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Id EmitDataConsume(EmitContext& ctx, u32 gds_addr, u32 binding) {
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const auto& buffer = ctx.buffers[binding];
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const auto [id, pointer_type] = buffer[EmitContext::BufferAlias::U32];
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const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, ctx.ConstU32(gds_addr));
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return ctx.OpAtomicIDecrement(ctx.U32[1], ptr, scope, semantics);
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}
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} // namespace Shader::Backend::SPIRV
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