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https://github.com/shadps4-emu/shadPS4.git
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98 lines
4.3 KiB
C++
98 lines
4.3 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::DS_SWIZZLE_B32(const GcnInst& inst) {
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const u8 offset0 = inst.control.ds.offset0;
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const u8 offset1 = inst.control.ds.offset1;
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const IR::U32 src{GetSrc(inst.src[1])};
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ASSERT(offset1 & 0x80);
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const IR::U32 lane_id = ir.LaneId();
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const IR::U32 id_in_group = ir.BitwiseAnd(lane_id, ir.Imm32(0b11));
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const IR::U32 base = ir.ShiftLeftLogical(id_in_group, ir.Imm32(1));
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const IR::U32 index =
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ir.IAdd(lane_id, ir.BitFieldExtract(ir.Imm32(offset0), base, ir.Imm32(2)));
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SetDst(inst.dst[0], ir.QuadShuffle(src, index));
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}
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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IR::VectorReg dst_reg{inst.dst[0].code};
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if (is_pair) {
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// Pair loads are either 32 or 64-bit. We assume 32-bit for now.
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::Value data0 = ir.LoadShared(bit_size, is_signed, addr0);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data0});
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} else {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 1)});
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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const IR::Value data1 = ir.LoadShared(bit_size, is_signed, addr1);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data1});
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} else {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 1)});
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}
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} else if (bit_size == 64) {
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr);
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
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} else {
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const IR::U32 data = IR::U32{ir.LoadShared(bit_size, is_signed, addr)};
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ir.SetVectorReg(dst_reg, data);
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}
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}
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void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::VectorReg data0{inst.src[1].code};
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const IR::VectorReg data1{inst.src[2].code};
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if (is_pair) {
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ASSERT(bit_size == 32);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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ir.WriteShared(32, ir.GetVectorReg(data0), addr0);
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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ir.WriteShared(32, ir.GetVectorReg(data1), addr1);
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} else if (bit_size == 64) {
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const IR::Value data =
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1));
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ir.WriteShared(bit_size, data, addr);
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} else {
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr);
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}
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}
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void Translator::S_BARRIER() {
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ir.Barrier();
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}
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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}
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void Translator::DS_MAX(int bit_size, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::U32 data{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::U32 current_max{ir.GetVectorReg(IR::VectorReg(inst.dst[0].code))};
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const IR::Value result =
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ir.ImageAtomicUMax(addr, data, current_max, Shader::IR::TextureInstInfo{});
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ir.SetVectorReg(IR::VectorReg(inst.dst[0].code), IR::U32{result});
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}
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void Translator::DS_MIN(int bit_size, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::U32 data{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::U32 current_min{ir.GetVectorReg(IR::VectorReg(inst.dst[0].code))};
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const IR::Value result =
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ir.ImageAtomicUMin(addr, data, current_min, Shader::IR::TextureInstInfo{});
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ir.SetVectorReg(IR::VectorReg(inst.dst[0].code), IR::U32{result});
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}
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} // namespace Shader::Gcn
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