mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-07-22 18:15:14 +00:00
625 lines
23 KiB
C++
625 lines
23 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/config.h"
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#include "common/io_file.h"
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#include "common/path_util.h"
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#include "shader_recompiler/frontend/decode.h"
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#include "shader_recompiler/frontend/fetch_shader.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/attribute.h"
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#include "shader_recompiler/ir/reg.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "shader_recompiler/runtime_info.h"
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#include "video_core/amdgpu/resource.h"
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#include "video_core/amdgpu/types.h"
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#define MAGIC_ENUM_RANGE_MIN 0
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#define MAGIC_ENUM_RANGE_MAX 1515
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#include <magic_enum/magic_enum.hpp>
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namespace Shader::Gcn {
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static IR::VectorReg IterateBarycentrics(const RuntimeInfo& runtime_info, auto&& set_attribute) {
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if (runtime_info.stage != Stage::Fragment) {
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return IR::VectorReg::V0;
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}
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u32 dst_vreg{};
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if (runtime_info.fs_info.addr_flags.persp_sample_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmoothSample, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmoothSample, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.persp_center_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmooth, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmooth, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.persp_centroid_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmoothCentroid, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordSmoothCentroid, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.persp_pull_model_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordPullModel, 0); // I/W
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordPullModel, 1); // J/W
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordPullModel, 2); // 1/W
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}
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if (runtime_info.fs_info.addr_flags.linear_sample_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPerspSample, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPerspSample, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.linear_center_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPersp, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPersp, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.linear_centroid_ena) {
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPerspCentroid, 0); // I
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set_attribute(dst_vreg++, IR::Attribute::BaryCoordNoPerspCentroid, 1); // J
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}
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if (runtime_info.fs_info.addr_flags.line_stipple_tex_ena) {
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++dst_vreg;
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}
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return IR::VectorReg(dst_vreg);
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}
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Translator::Translator(Info& info_, const RuntimeInfo& runtime_info_, const Profile& profile_)
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: info{info_}, runtime_info{runtime_info_}, profile{profile_},
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next_vgpr_num{runtime_info.num_allocated_vgprs} {
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IterateBarycentrics(runtime_info, [this](u32 vreg, IR::Attribute attrib, u32) {
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vgpr_to_interp[vreg] = attrib;
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});
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}
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void Translator::EmitPrologue(IR::Block* first_block) {
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ir = IR::IREmitter(*first_block, first_block->begin());
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ir.Prologue();
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ir.SetExec(ir.Imm1(true));
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < runtime_info.num_user_data; i++) {
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ir.SetScalarReg(dst_sreg, ir.GetUserData(dst_sreg));
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++dst_sreg;
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}
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (info.l_stage) {
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case LogicalStage::Vertex:
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// v0: vertex ID, always present
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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if (info.stage == Stage::Local) {
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// v1: rel patch ID
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if (runtime_info.num_input_vgprs > 0) {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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// v2: instance ID
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if (runtime_info.num_input_vgprs > 1) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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}
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} else {
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// v1: instance ID, step rate 0
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if (runtime_info.num_input_vgprs > 0) {
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if (runtime_info.vs_info.step_rate_0 != 0) {
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ir.SetVectorReg(dst_vreg++,
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ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
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ir.Imm32(runtime_info.vs_info.step_rate_0)));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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// v2: instance ID, step rate 1
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if (runtime_info.num_input_vgprs > 1) {
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if (runtime_info.vs_info.step_rate_1 != 0) {
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ir.SetVectorReg(dst_vreg++,
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ir.IDiv(ir.GetAttributeU32(IR::Attribute::InstanceId),
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ir.Imm32(runtime_info.vs_info.step_rate_1)));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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// v3: instance ID, plain
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if (runtime_info.num_input_vgprs > 2) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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}
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}
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break;
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case LogicalStage::Fragment:
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dst_vreg =
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IterateBarycentrics(runtime_info, [this](u32 vreg, IR::Attribute attrib, u32 comp) {
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ir.SetVectorReg(IR::VectorReg(vreg), ir.GetAttribute(attrib, comp));
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});
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if (runtime_info.fs_info.addr_flags.pos_x_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_x_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 0));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_y_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_y_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 1));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_z_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_z_float_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, 2));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.pos_w_float_ena) {
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if (runtime_info.fs_info.en_flags.pos_w_float_ena) {
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ir.SetVectorReg(dst_vreg++,
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ir.FPRecip(ir.GetAttribute(IR::Attribute::FragCoord, 3)));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0.0f));
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}
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}
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if (runtime_info.fs_info.addr_flags.front_face_ena) {
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if (runtime_info.fs_info.en_flags.front_face_ena) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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} else {
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ir.SetVectorReg(dst_vreg++, ir.Imm32(0));
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}
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}
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break;
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case LogicalStage::TessellationControl: {
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ir.SetVectorReg(IR::VectorReg::V0, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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// Should be laid out like:
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// [0:8]: patch id within VGT
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// [8:12]: output control point id
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ir.SetVectorReg(IR::VectorReg::V1,
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ir.GetAttributeU32(IR::Attribute::PackedHullInvocationInfo));
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break;
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}
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case LogicalStage::TessellationEval:
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ir.SetVectorReg(IR::VectorReg::V0,
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ir.GetAttribute(IR::Attribute::TessellationEvaluationPointU));
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ir.SetVectorReg(IR::VectorReg::V1,
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ir.GetAttribute(IR::Attribute::TessellationEvaluationPointV));
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// V2 is similar to PrimitiveID but not the same. It seems to only be used in
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// compiler-generated address calculations. Its probably the patch id within the
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// patches running locally on a given VGT (or CU, whichever is the granularity of LDS
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// memory)
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// Set to 0. See explanation in comment describing hull/domain passes
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ir.SetVectorReg(IR::VectorReg::V2, ir.Imm32(0u));
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// V3 is the actual PrimitiveID as intended by the shader author.
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ir.SetVectorReg(IR::VectorReg::V3, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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break;
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case LogicalStage::Compute:
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 0));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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if (runtime_info.cs_info.tgid_enable[0]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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}
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if (runtime_info.cs_info.tgid_enable[1]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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}
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if (runtime_info.cs_info.tgid_enable[2]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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}
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break;
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case LogicalStage::Geometry:
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switch (runtime_info.gs_info.out_primitive[0]) {
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case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
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ir.SetVectorReg(IR::VectorReg::V3, ir.Imm32(2u)); // vertex 2
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case AmdGpu::GsOutputPrimitiveType::LineStrip:
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ir.SetVectorReg(IR::VectorReg::V1, ir.Imm32(1u)); // vertex 1
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default:
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ir.SetVectorReg(IR::VectorReg::V0, ir.Imm32(0u)); // vertex 0
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break;
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}
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ir.SetVectorReg(IR::VectorReg::V2, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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break;
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default:
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UNREACHABLE_MSG("Unknown shader stage");
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}
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// Clear any scratch vgpr mappings for next shader.
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vgpr_map.clear();
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}
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IR::VectorReg Translator::GetScratchVgpr(u32 offset) {
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const auto [it, is_new] = vgpr_map.try_emplace(offset);
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if (is_new) {
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ASSERT_MSG(next_vgpr_num < 256, "Out of VGPRs");
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const auto new_vgpr = static_cast<IR::VectorReg>(next_vgpr_num++);
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it->second = new_vgpr;
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}
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return it->second;
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};
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template <typename T>
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T Translator::GetSrc(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F32>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm32(std::bit_cast<float>(value));
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} else {
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return ir.Imm32(std::bit_cast<u32>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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value = ir.GetScalarReg<T>(IR::ScalarReg(operand.code));
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break;
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case OperandField::VectorGPR:
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value = ir.GetVectorReg<T>(IR::VectorReg(operand.code));
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break;
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case OperandField::ConstZero:
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value = get_imm(0U);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(operand.code - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(operand.code);
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.f);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5f);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0f);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0f);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0f);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0f);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0f);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccLo());
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} else {
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value = ir.GetVccLo();
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}
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break;
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case OperandField::VccHi:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccHi());
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} else {
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value = ir.GetVccHi();
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}
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break;
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case OperandField::M0:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetM0());
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} else {
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value = ir.GetM0();
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}
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break;
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case OperandField::Scc:
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.BitCast<IR::U32>(ir.GetScc());
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}
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break;
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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} else {
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if (operand.input_modifier.abs) {
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value = ir.IAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.INeg(value);
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}
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}
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return value;
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}
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template IR::U32 Translator::GetSrc<IR::U32>(const InstOperand&);
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template IR::F32 Translator::GetSrc<IR::F32>(const InstOperand&);
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template <typename T>
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T Translator::GetSrc64(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F64>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm64(std::bit_cast<double>(value));
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} else {
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return ir.Imm64(std::bit_cast<u64>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR: {
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const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code));
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const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::VectorGPR: {
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const auto value_lo = ir.GetVectorReg(IR::VectorReg(operand.code));
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const auto value_hi = ir.GetVectorReg(IR::VectorReg(operand.code + 1));
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if constexpr (is_float) {
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value = ir.PackDouble2x32(ir.CompositeConstruct(value_lo, value_hi));
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::ConstZero:
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value = get_imm(0ULL);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(u64(operand.code));
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.0);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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value = ir.PackDouble2x32(ir.CompositeConstruct(ir.GetVccLo(), ir.GetVccHi()));
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(ir.GetVccLo(), ir.GetVccHi()));
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}
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break;
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case OperandField::VccHi:
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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}
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return value;
|
|
}
|
|
|
|
template IR::U64 Translator::GetSrc64<IR::U64>(const InstOperand&);
|
|
template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
|
|
|
|
void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
|
|
IR::U32F32 result = value;
|
|
if (value.Type() == IR::Type::F32) {
|
|
if (operand.output_modifier.multiplier != 0.f) {
|
|
result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
|
|
}
|
|
if (operand.output_modifier.clamp) {
|
|
result = ir.FPSaturate(value);
|
|
}
|
|
}
|
|
|
|
switch (operand.field) {
|
|
case OperandField::ScalarGPR:
|
|
return ir.SetScalarReg(IR::ScalarReg(operand.code), result);
|
|
case OperandField::VectorGPR:
|
|
return ir.SetVectorReg(IR::VectorReg(operand.code), result);
|
|
case OperandField::VccLo:
|
|
return ir.SetVccLo(result);
|
|
case OperandField::VccHi:
|
|
return ir.SetVccHi(result);
|
|
case OperandField::M0:
|
|
return ir.SetM0(result);
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
void Translator::SetDst64(const InstOperand& operand, const IR::U64F64& value_raw) {
|
|
IR::U64F64 value_untyped = value_raw;
|
|
|
|
const bool is_float = value_raw.Type() == IR::Type::F64 || value_raw.Type() == IR::Type::F32;
|
|
if (is_float) {
|
|
if (operand.output_modifier.multiplier != 0.f) {
|
|
value_untyped =
|
|
ir.FPMul(value_untyped, ir.Imm64(f64(operand.output_modifier.multiplier)));
|
|
}
|
|
if (operand.output_modifier.clamp) {
|
|
value_untyped = ir.FPSaturate(value_raw);
|
|
}
|
|
}
|
|
|
|
const IR::Value unpacked{is_float ? ir.UnpackDouble2x32(IR::F64{value_untyped})
|
|
: ir.UnpackUint2x32(IR::U64{value_untyped})};
|
|
const IR::U32 lo{ir.CompositeExtract(unpacked, 0U)};
|
|
const IR::U32 hi{ir.CompositeExtract(unpacked, 1U)};
|
|
switch (operand.field) {
|
|
case OperandField::ScalarGPR:
|
|
ir.SetScalarReg(IR::ScalarReg(operand.code + 1), hi);
|
|
return ir.SetScalarReg(IR::ScalarReg(operand.code), lo);
|
|
case OperandField::VectorGPR:
|
|
ir.SetVectorReg(IR::VectorReg(operand.code + 1), hi);
|
|
return ir.SetVectorReg(IR::VectorReg(operand.code), lo);
|
|
case OperandField::VccLo:
|
|
ir.SetVccLo(lo);
|
|
return ir.SetVccHi(hi);
|
|
case OperandField::VccHi:
|
|
UNREACHABLE();
|
|
case OperandField::M0:
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
void Translator::EmitFetch(const GcnInst& inst) {
|
|
const auto code_sgpr_base = inst.src[0].code;
|
|
|
|
// The fetch shader must be inlined to access as regular buffers, so that
|
|
// bounds checks can be emitted to emulate robust buffer access.
|
|
if (!profile.supports_robust_buffer_access) {
|
|
const auto* code = GetFetchShaderCode(info, code_sgpr_base);
|
|
GcnCodeSlice slice(code, code + std::numeric_limits<u32>::max());
|
|
GcnDecodeContext decoder;
|
|
|
|
// Decode and save instructions
|
|
u32 sub_pc = 0;
|
|
while (!slice.atEnd()) {
|
|
const auto sub_inst = decoder.decodeInstruction(slice);
|
|
if (sub_inst.opcode == Opcode::S_SETPC_B64) {
|
|
// Assume we're swapping back to the main shader.
|
|
break;
|
|
}
|
|
TranslateInstruction(sub_inst, sub_pc++);
|
|
}
|
|
return;
|
|
}
|
|
|
|
info.has_fetch_shader = true;
|
|
info.fetch_shader_sgpr_base = code_sgpr_base;
|
|
|
|
const auto fetch_data = ParseFetchShader(info);
|
|
ASSERT(fetch_data.has_value());
|
|
|
|
if (Config::dumpShaders()) {
|
|
using namespace Common::FS;
|
|
const auto dump_dir = GetUserPath(PathType::ShaderDir) / "dumps";
|
|
if (!std::filesystem::exists(dump_dir)) {
|
|
std::filesystem::create_directories(dump_dir);
|
|
}
|
|
const auto filename = fmt::format("vs_{:#018x}.fetch.bin", info.pgm_hash);
|
|
const auto file = IOFile{dump_dir / filename, FileAccessMode::Write};
|
|
file.WriteRaw<u8>(fetch_data->code, fetch_data->size);
|
|
}
|
|
|
|
for (const auto& attrib : fetch_data->attributes) {
|
|
const IR::Attribute attr{IR::Attribute::Param0 + attrib.semantic};
|
|
IR::VectorReg dst_reg{attrib.dest_vgpr};
|
|
|
|
// Read the V# of the attribute to figure out component number and type.
|
|
const auto buffer = info.ReadUdReg<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
|
|
const auto values =
|
|
ir.CompositeConstruct(ir.GetAttribute(attr, 0), ir.GetAttribute(attr, 1),
|
|
ir.GetAttribute(attr, 2), ir.GetAttribute(attr, 3));
|
|
const auto converted =
|
|
IR::ApplyReadNumberConversionVec4(ir, values, buffer.GetNumberConversion());
|
|
const auto swizzled = ApplySwizzle(ir, converted, buffer.DstSelect());
|
|
for (u32 i = 0; i < 4; i++) {
|
|
ir.SetVectorReg(dst_reg++, IR::F32{ir.CompositeExtract(swizzled, i)});
|
|
}
|
|
}
|
|
}
|
|
|
|
void Translator::LogMissingOpcode(const GcnInst& inst) {
|
|
LOG_ERROR(Render_Recompiler, "Unknown opcode {} ({}, category = {})",
|
|
magic_enum::enum_name(inst.opcode), u32(inst.opcode),
|
|
magic_enum::enum_name(inst.category));
|
|
info.translation_failed = true;
|
|
}
|
|
|
|
void Translator::Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list) {
|
|
if (inst_list.empty()) {
|
|
return;
|
|
}
|
|
ir = IR::IREmitter{*block, block->begin()};
|
|
for (const auto& inst : inst_list) {
|
|
pc += inst.length;
|
|
|
|
// Special case for emitting fetch shader.
|
|
if (inst.opcode == Opcode::S_SWAPPC_B64) {
|
|
ASSERT(info.stage == Stage::Vertex || info.stage == Stage::Export ||
|
|
info.stage == Stage::Local);
|
|
EmitFetch(inst);
|
|
continue;
|
|
}
|
|
|
|
TranslateInstruction(inst, pc);
|
|
}
|
|
}
|
|
|
|
void Translator::TranslateInstruction(const GcnInst& inst, const u32 pc) {
|
|
// Emit instructions for each category.
|
|
switch (inst.category) {
|
|
case InstCategory::DataShare:
|
|
EmitDataShare(inst);
|
|
break;
|
|
case InstCategory::VectorInterpolation:
|
|
EmitVectorInterpolation(inst);
|
|
break;
|
|
case InstCategory::ScalarMemory:
|
|
EmitScalarMemory(inst);
|
|
break;
|
|
case InstCategory::VectorMemory:
|
|
EmitVectorMemory(inst);
|
|
break;
|
|
case InstCategory::Export:
|
|
EmitExport(inst);
|
|
break;
|
|
case InstCategory::FlowControl:
|
|
EmitFlowControl(pc, inst);
|
|
break;
|
|
case InstCategory::ScalarALU:
|
|
EmitScalarAlu(inst);
|
|
break;
|
|
case InstCategory::VectorALU:
|
|
EmitVectorAlu(inst);
|
|
break;
|
|
case InstCategory::DebugProfile:
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
} // namespace Shader::Gcn
|