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https://github.com/shadps4-emu/shadPS4.git
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100 lines
3.3 KiB
C++
100 lines
3.3 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <algorithm>
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#include <iterator>
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#include <boost/container/small_vector.hpp>
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#include "common/assert.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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#include "shader_recompiler/ir/debug_print.h"
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#include "shader_recompiler/ir/opcodes.h"
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namespace Shader::Backend::SPIRV {
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void EmitPrologue(EmitContext& ctx) {
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ctx.DefineBufferOffsets();
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}
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void ConvertDepthMode(EmitContext& ctx) {
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const Id type{ctx.F32[1]};
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const Id position{ctx.OpLoad(ctx.F32[4], ctx.output_position)};
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const Id z{ctx.OpCompositeExtract(type, position, 2u)};
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const Id w{ctx.OpCompositeExtract(type, position, 3u)};
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const Id screen_depth{ctx.OpFMul(type, ctx.OpFAdd(type, z, w), ctx.Constant(type, 0.5f))};
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const Id vector{ctx.OpCompositeInsert(ctx.F32[4], screen_depth, position, 2u)};
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ctx.OpStore(ctx.output_position, vector);
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}
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void EmitEpilogue(EmitContext& ctx) {
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if (ctx.stage == Stage::Vertex && ctx.runtime_info.vs_info.emulate_depth_negative_one_to_one) {
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ConvertDepthMode(ctx);
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}
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}
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void EmitDiscard(EmitContext& ctx) {
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ctx.OpDemoteToHelperInvocationEXT();
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}
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void EmitDiscardCond(EmitContext& ctx, Id condition) {
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const Id kill_label{ctx.OpLabel()};
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const Id merge_label{ctx.OpLabel()};
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ctx.OpSelectionMerge(merge_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(condition, kill_label, merge_label);
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ctx.AddLabel(kill_label);
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ctx.OpDemoteToHelperInvocationEXT();
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ctx.OpBranch(merge_label);
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ctx.AddLabel(merge_label);
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}
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void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream) {
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throw NotImplementedException("Geometry streams");
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}
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void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream) {
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throw NotImplementedException("Geometry streams");
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}
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static bool isEmptyInst(IR::Value val) {
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if (auto* inst = val.TryInstRecursive()) {
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return inst->GetOpcode() == IR::Opcode::Void;
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}
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return false;
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}
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void EmitVaArg(EmitContext& ctx, IR::Inst* inst, Id arg, Id next) {
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IR::Value next_val = inst->Arg(1);
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u32 va_arglist_idx;
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if (isEmptyInst(next_val)) {
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va_arglist_idx = ctx.va_arg_lists.size();
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ctx.va_arg_lists.emplace_back();
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} else {
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va_arglist_idx = next_val.Inst()->Flags<VariadicArgInfo>().va_arg_idx;
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}
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ctx.va_arg_lists[va_arglist_idx].push_back(arg);
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auto va_info = inst->Flags<VariadicArgInfo>();
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va_info.va_arg_idx.Assign(va_arglist_idx);
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inst->SetFlags(va_info);
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}
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Id EmitStringLiteral(EmitContext& ctx, IR::Inst* inst) {
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// ctx.
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return ctx.String(inst->StringLiteral());
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}
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void EmitDebugPrint(EmitContext& ctx, IR::Inst* inst, Id fmt) {
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IR::Value arglist = inst->Arg(1);
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boost::container::small_vector<Id, 4> fmt_arg_operands;
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if (!isEmptyInst(arglist)) {
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u32 va_arglist_idx = arglist.Inst()->Flags<VariadicArgInfo>().va_arg_idx;
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const auto& va_arglist = ctx.va_arg_lists[va_arglist_idx];
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// reverse the order
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std::copy(va_arglist.rbegin(), va_arglist.rend(), std::back_inserter(fmt_arg_operands));
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}
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ctx.OpDebugPrintf(fmt, fmt_arg_operands);
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}
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} // namespace Shader::Backend::SPIRV
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