mirror of
https://github.com/shadps4-emu/shadPS4.git
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6a4cf2763a
DONT MERGE set log file to /dev/null DONT MERGE linux pthread bb fix save work DONT MERGE dump ir save more work fix mistake with ES shader skip list add input patch control points dynamic state random stuff
273 lines
11 KiB
C++
273 lines
11 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/runtime_info.h"
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#pragma clang optimize off
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/reg.h"
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namespace Shader::Gcn {
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void Translator::EmitDataShare(const GcnInst& inst) {
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switch (inst.opcode) {
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// DS
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case Opcode::DS_ADD_U32:
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return DS_ADD_U32(inst, false);
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case Opcode::DS_MIN_I32:
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return DS_MIN_U32(inst, true, false);
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case Opcode::DS_MAX_I32:
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return DS_MAX_U32(inst, true, false);
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case Opcode::DS_MIN_U32:
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return DS_MIN_U32(inst, false, false);
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case Opcode::DS_MAX_U32:
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return DS_MAX_U32(inst, false, false);
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case Opcode::DS_AND_B32:
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return DS_AND_B32(inst, false);
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case Opcode::DS_OR_B32:
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return DS_OR_B32(inst, false);
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case Opcode::DS_XOR_B32:
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return DS_XOR_B32(inst, false);
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case Opcode::DS_WRITE_B32:
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return DS_WRITE(32, false, false, false, inst);
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case Opcode::DS_WRITE2_B32:
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return DS_WRITE(32, false, true, false, inst);
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case Opcode::DS_WRITE2ST64_B32:
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return DS_WRITE(32, false, true, true, inst);
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case Opcode::DS_ADD_RTN_U32:
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return DS_ADD_U32(inst, true);
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case Opcode::DS_MIN_RTN_U32:
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return DS_MIN_U32(inst, false, true);
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case Opcode::DS_MAX_RTN_U32:
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return DS_MAX_U32(inst, false, true);
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case Opcode::DS_AND_RTN_B32:
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return DS_AND_B32(inst, true);
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case Opcode::DS_OR_RTN_B32:
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return DS_OR_B32(inst, true);
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case Opcode::DS_XOR_RTN_B32:
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return DS_XOR_B32(inst, true);
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case Opcode::DS_SWIZZLE_B32:
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return DS_SWIZZLE_B32(inst);
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case Opcode::DS_READ_B32:
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return DS_READ(32, false, false, false, inst);
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case Opcode::DS_READ2_B32:
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return DS_READ(32, false, true, false, inst);
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case Opcode::DS_READ2ST64_B32:
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return DS_READ(32, false, true, true, inst);
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case Opcode::DS_CONSUME:
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return DS_CONSUME(inst);
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case Opcode::DS_APPEND:
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return DS_APPEND(inst);
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case Opcode::DS_WRITE_B64:
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return DS_WRITE(64, false, false, false, inst);
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case Opcode::DS_WRITE2_B64:
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return DS_WRITE(64, false, true, false, inst);
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case Opcode::DS_READ_B64:
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return DS_READ(64, false, false, false, inst);
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case Opcode::DS_READ2_B64:
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return DS_READ(64, false, true, false, inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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// VOP2
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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const IR::U32 value{GetSrc(inst.src[0])};
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if (info.l_stage == LogicalStage::Compute ||
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info.l_stage == LogicalStage::TessellationControl) {
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SetDst(inst.dst[0], ir.ReadFirstLane(value));
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} else {
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SetDst(inst.dst[0], value);
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}
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}
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void Translator::V_READLANE_B32(const GcnInst& inst) {
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const IR::U32 value{GetSrc(inst.src[0])};
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const IR::U32 lane{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.ReadLane(value, lane));
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}
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void Translator::V_WRITELANE_B32(const GcnInst& inst) {
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const IR::VectorReg dst{inst.dst[0].code};
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const IR::U32 value{GetSrc(inst.src[0])};
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const IR::U32 lane{GetSrc(inst.src[1])};
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const IR::U32 old_value{GetSrc(inst.dst[0])};
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ir.SetVectorReg(dst, ir.WriteLane(old_value, value, lane));
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}
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// DS
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void Translator::DS_ADD_U32(const GcnInst& inst, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIAdd(addr_offset, data);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_MIN_U32(const GcnInst& inst, bool is_signed, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIMin(addr_offset, data, is_signed);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_MAX_U32(const GcnInst& inst, bool is_signed, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIMax(addr_offset, data, is_signed);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_AND_B32(const GcnInst& inst, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicAnd(addr_offset, data);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_OR_B32(const GcnInst& inst, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicOr(addr_offset, data);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_XOR_B32(const GcnInst& inst, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicXor(addr_offset, data);
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if (rtn) {
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SetDst(inst.dst[0], IR::U32{original_val});
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}
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}
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void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, bool stride64,
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const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::VectorReg data0{inst.src[1].code};
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const IR::VectorReg data1{inst.src[2].code};
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if (is_pair) {
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const u32 adj = (bit_size == 32 ? 4 : 8) * (stride64 ? 64 : 1);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data0), addr0);
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} else {
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ir.WriteShared(
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64, ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1)),
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addr0);
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data1), addr1);
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} else {
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ir.WriteShared(
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64, ir.CompositeConstruct(ir.GetVectorReg(data1), ir.GetVectorReg(data1 + 1)),
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addr1);
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}
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} else if (bit_size == 64) {
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::Value data =
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1));
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ir.WriteShared(bit_size, data, addr0);
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} else {
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr0);
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}
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}
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void Translator::DS_SWIZZLE_B32(const GcnInst& inst) {
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const u8 offset0 = inst.control.ds.offset0;
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const u8 offset1 = inst.control.ds.offset1;
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const IR::U32 src{GetSrc(inst.src[0])};
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// ASSERT(offset1 & 0x80);
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const IR::U32 lane_id = ir.LaneId();
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const IR::U32 id_in_group = ir.BitwiseAnd(lane_id, ir.Imm32(0b11));
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const IR::U32 base = ir.ShiftLeftLogical(id_in_group, ir.Imm32(1));
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const IR::U32 index = ir.BitFieldExtract(ir.Imm32(offset0), base, ir.Imm32(2));
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SetDst(inst.dst[0], ir.QuadShuffle(src, index));
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}
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, bool stride64,
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const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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IR::VectorReg dst_reg{inst.dst[0].code};
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if (is_pair) {
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// Pair loads are either 32 or 64-bit
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const u32 adj = (bit_size == 32 ? 4 : 8) * (stride64 ? 64 : 1);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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const IR::Value data0 = ir.LoadShared(bit_size, is_signed, addr0);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data0});
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} else {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 1)});
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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const IR::Value data1 = ir.LoadShared(bit_size, is_signed, addr1);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data1});
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} else {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 1)});
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}
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} else if (bit_size == 64) {
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr0);
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
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} else {
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::U32 data = IR::U32{ir.LoadShared(bit_size, is_signed, addr0)};
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ir.SetVectorReg(dst_reg, data);
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}
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}
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void Translator::DS_APPEND(const GcnInst& inst) {
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataAppend(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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void Translator::DS_CONSUME(const GcnInst& inst) {
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataConsume(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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} // namespace Shader::Gcn
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