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27cbd6647f
* shader_recompiler: Reorganize data share operations and implement GDS bit * Review comments
303 lines
12 KiB
C++
303 lines
12 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/reg.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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void Translator::EmitDataShare(const GcnInst& inst) {
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switch (inst.opcode) {
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// DS
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case Opcode::DS_ADD_U32:
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return DS_OP(inst, AtomicOp::Add, false);
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case Opcode::DS_ADD_U64:
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return DS_OP<IR::U64>(inst, AtomicOp::Add, false);
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case Opcode::DS_SUB_U32:
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return DS_OP(inst, AtomicOp::Sub, false);
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case Opcode::DS_INC_U32:
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return DS_OP(inst, AtomicOp::Inc, false);
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case Opcode::DS_DEC_U32:
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return DS_OP(inst, AtomicOp::Dec, false);
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case Opcode::DS_MIN_I32:
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return DS_OP(inst, AtomicOp::Smin, false);
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case Opcode::DS_MAX_I32:
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return DS_OP(inst, AtomicOp::Smax, false);
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case Opcode::DS_MIN_U32:
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return DS_OP(inst, AtomicOp::Umin, false);
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case Opcode::DS_MAX_U32:
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return DS_OP(inst, AtomicOp::Umax, false);
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case Opcode::DS_AND_B32:
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return DS_OP(inst, AtomicOp::And, false);
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case Opcode::DS_OR_B32:
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return DS_OP(inst, AtomicOp::Or, false);
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case Opcode::DS_XOR_B32:
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return DS_OP(inst, AtomicOp::Xor, false);
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case Opcode::DS_WRITE_B32:
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return DS_WRITE(32, false, false, false, inst);
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case Opcode::DS_WRITE2_B32:
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return DS_WRITE(32, false, true, false, inst);
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case Opcode::DS_WRITE2ST64_B32:
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return DS_WRITE(32, false, true, true, inst);
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case Opcode::DS_ADD_RTN_U32:
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return DS_OP(inst, AtomicOp::Add, true);
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case Opcode::DS_SUB_RTN_U32:
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return DS_OP(inst, AtomicOp::Sub, true);
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case Opcode::DS_MIN_RTN_U32:
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return DS_OP(inst, AtomicOp::Umin, true);
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case Opcode::DS_MAX_RTN_U32:
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return DS_OP(inst, AtomicOp::Umax, true);
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case Opcode::DS_AND_RTN_B32:
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return DS_OP(inst, AtomicOp::And, true);
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case Opcode::DS_OR_RTN_B32:
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return DS_OP(inst, AtomicOp::Or, true);
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case Opcode::DS_XOR_RTN_B32:
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return DS_OP(inst, AtomicOp::Xor, true);
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case Opcode::DS_SWIZZLE_B32:
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return DS_SWIZZLE_B32(inst);
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case Opcode::DS_READ_B32:
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return DS_READ(32, false, false, false, inst);
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case Opcode::DS_READ2_B32:
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return DS_READ(32, false, true, false, inst);
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case Opcode::DS_READ2ST64_B32:
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return DS_READ(32, false, true, true, inst);
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case Opcode::DS_READ_U16:
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return DS_READ(16, false, false, false, inst);
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case Opcode::DS_CONSUME:
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return DS_CONSUME(inst);
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case Opcode::DS_APPEND:
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return DS_APPEND(inst);
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case Opcode::DS_WRITE_B16:
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return DS_WRITE(16, false, false, false, inst);
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case Opcode::DS_WRITE_B64:
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return DS_WRITE(64, false, false, false, inst);
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case Opcode::DS_WRITE2_B64:
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return DS_WRITE(64, false, true, false, inst);
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case Opcode::DS_WRITE2ST64_B64:
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return DS_WRITE(64, false, true, true, inst);
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case Opcode::DS_READ_B64:
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return DS_READ(64, false, false, false, inst);
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case Opcode::DS_READ2_B64:
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return DS_READ(64, false, true, false, inst);
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case Opcode::DS_READ2ST64_B64:
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return DS_READ(64, false, true, true, inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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// VOP2
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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const IR::U32 value{GetSrc(inst.src[0])};
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if (info.l_stage == LogicalStage::Compute ||
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info.l_stage == LogicalStage::TessellationControl) {
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SetDst(inst.dst[0], ir.ReadFirstLane(value));
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} else {
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SetDst(inst.dst[0], value);
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}
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}
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void Translator::V_READLANE_B32(const GcnInst& inst) {
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const IR::U32 value{GetSrc(inst.src[0])};
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const IR::U32 lane{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.ReadLane(value, lane));
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}
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void Translator::V_WRITELANE_B32(const GcnInst& inst) {
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const IR::VectorReg dst{inst.dst[0].code};
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const IR::U32 value{GetSrc(inst.src[0])};
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const IR::U32 lane{GetSrc(inst.src[1])};
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const IR::U32 old_value{GetSrc(inst.dst[0])};
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ir.SetVectorReg(dst, ir.WriteLane(old_value, value, lane));
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}
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// DS
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template <typename T>
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void Translator::DS_OP(const GcnInst& inst, AtomicOp op, bool rtn) {
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const bool is_gds = inst.control.ds.gds;
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const IR::U32 addr{GetSrc(inst.src[0])};
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const T data = [&] {
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if (op == AtomicOp::Inc || op == AtomicOp::Dec) {
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return T{};
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}
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if constexpr (std::is_same_v<T, IR::U32>) {
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return GetSrc(inst.src[1]);
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} else {
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return GetSrc64(inst.src[1]);
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}
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}();
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const T original_val = [&] -> T {
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switch (op) {
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case AtomicOp::Add:
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return ir.SharedAtomicIAdd(addr_offset, data, is_gds);
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case AtomicOp::Umin:
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return ir.SharedAtomicIMin(addr_offset, data, false, is_gds);
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case AtomicOp::Smin:
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return ir.SharedAtomicIMin(addr_offset, data, true, is_gds);
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case AtomicOp::Umax:
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return ir.SharedAtomicIMax(addr_offset, data, false, is_gds);
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case AtomicOp::Smax:
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return ir.SharedAtomicIMax(addr_offset, data, true, is_gds);
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case AtomicOp::And:
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return ir.SharedAtomicAnd(addr_offset, data, is_gds);
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case AtomicOp::Or:
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return ir.SharedAtomicOr(addr_offset, data, is_gds);
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case AtomicOp::Xor:
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return ir.SharedAtomicXor(addr_offset, data, is_gds);
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case AtomicOp::Sub:
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return ir.SharedAtomicISub(addr_offset, data, is_gds);
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case AtomicOp::Inc:
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return ir.SharedAtomicInc<T>(addr_offset, is_gds);
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case AtomicOp::Dec:
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return ir.SharedAtomicDec<T>(addr_offset, is_gds);
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default:
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UNREACHABLE();
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}
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}();
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if (rtn) {
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if constexpr (std::is_same_v<T, IR::U32>) {
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SetDst(inst.dst[0], original_val);
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} else {
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SetDst64(inst.dst[0], original_val);
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}
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}
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}
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void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, bool stride64,
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const GcnInst& inst) {
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const bool is_gds = inst.control.ds.gds;
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::VectorReg data0{inst.src[1].code};
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const IR::VectorReg data1{inst.src[2].code};
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const u32 offset = (inst.control.ds.offset1 << 8u) + inst.control.ds.offset0;
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if (info.stage == Stage::Fragment) {
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ASSERT_MSG(!is_pair && bit_size == 32 && offset % 256 == 0,
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"Unexpected shared memory offset alignment: {}", offset);
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ir.SetVectorReg(GetScratchVgpr(offset), ir.GetVectorReg(data0));
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return;
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}
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if (is_pair) {
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const u32 adj = (bit_size == 32 ? 4 : 8) * (stride64 ? 64 : 1);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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if (bit_size == 64) {
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ir.WriteShared(64,
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ir.PackUint2x32(ir.CompositeConstruct(ir.GetVectorReg(data0),
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ir.GetVectorReg(data0 + 1))),
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addr0, is_gds);
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} else if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data0), addr0, is_gds);
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} else if (bit_size == 16) {
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ir.WriteShared(16, ir.UConvert(16, ir.GetVectorReg(data0)), addr0, is_gds);
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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if (bit_size == 64) {
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ir.WriteShared(64,
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ir.PackUint2x32(ir.CompositeConstruct(ir.GetVectorReg(data1),
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ir.GetVectorReg(data1 + 1))),
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addr1, is_gds);
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} else if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data1), addr1, is_gds);
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} else if (bit_size == 16) {
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ir.WriteShared(16, ir.UConvert(16, ir.GetVectorReg(data1)), addr1, is_gds);
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}
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} else {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(offset));
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if (bit_size == 64) {
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const IR::Value data =
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1));
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ir.WriteShared(bit_size, ir.PackUint2x32(data), addr0, is_gds);
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} else if (bit_size == 32) {
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr0, is_gds);
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} else if (bit_size == 16) {
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ir.WriteShared(bit_size, ir.UConvert(16, ir.GetVectorReg(data0)), addr0, is_gds);
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}
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}
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}
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, bool stride64,
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const GcnInst& inst) {
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const bool is_gds = inst.control.ds.gds;
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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IR::VectorReg dst_reg{inst.dst[0].code};
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const u32 offset = (inst.control.ds.offset1 << 8u) + inst.control.ds.offset0;
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if (info.stage == Stage::Fragment) {
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ASSERT_MSG(!is_pair && bit_size == 32 && offset % 256 == 0,
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"Unexpected shared memory offset alignment: {}", offset);
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ir.SetVectorReg(dst_reg, ir.GetVectorReg(GetScratchVgpr(offset)));
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return;
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}
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if (is_pair) {
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// Pair loads are either 32 or 64-bit
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const u32 adj = (bit_size == 32 ? 4 : 8) * (stride64 ? 64 : 1);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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const IR::Value data0 = ir.LoadShared(bit_size, is_signed, addr0, is_gds);
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if (bit_size == 64) {
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const auto vector = ir.UnpackUint2x32(IR::U64{data0});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(vector, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(vector, 1)});
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} else if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data0});
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} else if (bit_size == 16) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.UConvert(32, IR::U16{data0})});
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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const IR::Value data1 = ir.LoadShared(bit_size, is_signed, addr1, is_gds);
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if (bit_size == 64) {
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const auto vector = ir.UnpackUint2x32(IR::U64{data1});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(vector, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(vector, 1)});
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} else if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data1});
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} else if (bit_size == 16) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.UConvert(32, IR::U16{data1})});
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}
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} else {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(offset));
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr0, is_gds);
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if (bit_size == 64) {
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const auto vector = ir.UnpackUint2x32(IR::U64{data});
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(vector, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(vector, 1)});
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} else if (bit_size == 32) {
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ir.SetVectorReg(dst_reg, IR::U32{data});
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} else if (bit_size == 16) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.UConvert(32, IR::U16{data})});
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}
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}
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}
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void Translator::DS_SWIZZLE_B32(const GcnInst& inst) {
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const u8 offset0 = inst.control.ds.offset0;
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const u8 offset1 = inst.control.ds.offset1;
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const IR::U32 src{GetSrc(inst.src[0])};
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// ASSERT(offset1 & 0x80);
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const IR::U32 lane_id = ir.LaneId();
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const IR::U32 id_in_group = ir.BitwiseAnd(lane_id, ir.Imm32(0b11));
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const IR::U32 base = ir.ShiftLeftLogical(id_in_group, ir.Imm32(1));
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const IR::U32 index = ir.BitFieldExtract(ir.Imm32(offset0), base, ir.Imm32(2));
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SetDst(inst.dst[0], ir.QuadShuffle(src, index));
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}
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void Translator::DS_APPEND(const GcnInst& inst) {
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataAppend(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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void Translator::DS_CONSUME(const GcnInst& inst) {
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataConsume(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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} // namespace Shader::Gcn
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