mirror of
https://github.com/shadps4-emu/shadPS4.git
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a7c9bfa5c5
* translator: Implemtn f32 to f16 convert * shader_recompiler: Add bit instructions * shader_recompiler: More data share instructions * shader_recompiler: Remove exec contexts, fix S_MOV_B64 * shader_recompiler: Split instruction parsing into categories * shader_recompiler: Better BFS search * shader_recompiler: Constant propagation pass for cmp_class_f32 * shader_recompiler: Partial readfirstlane implementation * shader_recompiler: Stub readlane/writelane only for non-compute * hack: Fix swizzle on RDR * Will properly fix this when merging this * clang format * address_space: Bump user area size to full * shader_recompiler: V_INTERP_MOV_F32 * Should work the same as spirv will emit flat decoration on demand * kernel: Add MAP_OP_MAP_FLEXIBLE * image_view: Attempt to apply storage swizzle on format * vk_scheduler: Barrier attachments on renderpass end * clang format * liverpool: cs state backup * shader_recompiler: More instructions and formats * vector_alu: Proper V_MBCNT_U32_B32 * shader_recompiler: Port some dark souls things * file_system: Implement sceKernelRename * more formats * clang format * resource_tracking_pass: Back to assert * translate: Tracedata * kernel: Remove tracy lock * Solves random crashes in Dark Souls * code: Review comments
298 lines
9.2 KiB
C++
298 lines
9.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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void SetZeroFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
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// IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)};
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// if (!zero) {
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// return;
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// }
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// zero->SetDefinition(ctx.OpIEqual(ctx.U1[1], result, ctx.u32_zero_value));
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// zero->Invalidate();
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}
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void SetSignFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
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// IR::Inst* const sign{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)};
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// if (!sign) {
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// return;
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// }
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// sign->SetDefinition(ctx.OpSLessThan(ctx.U1[1], result, ctx.u32_zero_value));
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// sign->Invalidate();
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}
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} // Anonymous namespace
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return ctx.OpIAdd(ctx.U32[1], a, b);
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// Id result{};
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// if (IR::Inst* const carry{inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp)}) {
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// const Id carry_type{ctx.TypeStruct(ctx.U32[1], ctx.U32[1])};
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// const Id carry_result{ctx.OpIAddCarry(carry_type, a, b)};
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// result = ctx.OpCompositeExtract(ctx.U32[1], carry_result, 0U);
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// const Id carry_value{ctx.OpCompositeExtract(ctx.U32[1], carry_result, 1U)};
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// carry->SetDefinition(ctx.OpINotEqual(ctx.U1[1][1], carry_value, ctx.u32_zero_value));
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// carry->Invalidate();
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//} else {
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// result = ctx.OpIAdd(ctx.U32[1], a, b);
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//}
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// SetZeroFlag(ctx, inst, result);
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// SetSignFlag(ctx, inst, result);
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// if (IR::Inst * overflow{inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
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// // https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
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// constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
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// const Id is_positive{ctx.OpSGreaterThanEqual(ctx.U1[1], a, ctx.u32_zero_value)};
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// const Id sub_a{ctx.OpISub(ctx.U32[1], ctx.Const(s32_max), a)};
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// const Id positive_test{ctx.OpSGreaterThan(ctx.U1[1], b, sub_a)};
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// const Id negative_test{ctx.OpSLessThan(ctx.U1[1], b, sub_a)};
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// const Id carry_flag{ctx.OpSelect(ctx.U1[1], is_positive, positive_test, negative_test)};
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// overflow->SetDefinition(carry_flag);
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// overflow->Invalidate();
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//}
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// return result;
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}
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Id EmitIAdd64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIAdd(ctx.U64, a, b);
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}
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Id EmitIAddCary32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIAddCarry(ctx.full_result_u32x2, a, b);
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}
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Id EmitISub32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U32[1], a, b);
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}
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Id EmitISub64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U64, a, b);
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}
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Id EmitSMulExt(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMulExtended(ctx.full_result_i32x2, a, b);
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}
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Id EmitUMulExt(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMulExtended(ctx.full_result_u32x2, a, b);
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}
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Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIMul(ctx.U32[1], a, b);
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}
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Id EmitIMul64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIMul(ctx.U64, a, b);
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}
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Id EmitSDiv32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSDiv(ctx.U32[1], a, b);
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}
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Id EmitUDiv32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUDiv(ctx.U32[1], a, b);
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}
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Id EmitINeg32(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U32[1], value);
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}
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Id EmitINeg64(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U64, value);
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}
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Id EmitIAbs32(EmitContext& ctx, Id value) {
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return ctx.OpSAbs(ctx.U32[1], value);
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}
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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}
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Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U64, base, shift);
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}
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Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U32[1], base, shift);
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}
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Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U64, base, shift);
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}
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift);
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}
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Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
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}
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Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseAnd(ctx.U32[1], a, b)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitwiseOr64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseOr(ctx.U64, a, b)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseXor(ctx.U32[1], a, b)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) {
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return ctx.OpBitFieldInsert(ctx.U32[1], base, insert, offset, count);
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}
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Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitReverse32(EmitContext& ctx, Id value) {
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return ctx.OpBitReverse(ctx.U32[1], value);
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}
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Id EmitBitCount32(EmitContext& ctx, Id value) {
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return ctx.OpBitCount(ctx.U32[1], value);
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}
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Id EmitBitwiseNot32(EmitContext& ctx, Id value) {
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return ctx.OpNot(ctx.U32[1], value);
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}
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Id EmitFindSMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindSMsb(ctx.U32[1], value);
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}
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Id EmitFindUMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindUMsb(ctx.U32[1], value);
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}
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Id EmitFindILsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindILsb(ctx.U32[1], value);
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}
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Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMin(ctx.U32[1], a, b);
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}
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Id EmitUMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMin(ctx.U32[1], a, b);
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}
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Id EmitSMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMax(ctx.U32[1], a, b);
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}
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Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMax(ctx.U32[1], a, b);
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}
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Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
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Id result{};
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if (ctx.profile.has_broken_spirv_clamp) {
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value = ctx.OpBitcast(ctx.S32[1], value);
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min = ctx.OpBitcast(ctx.S32[1], min);
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max = ctx.OpBitcast(ctx.S32[1], max);
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result = ctx.OpSMax(ctx.S32[1], ctx.OpSMin(ctx.S32[1], value, max), min);
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result = ctx.OpBitcast(ctx.U32[1], result);
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} else {
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result = ctx.OpSClamp(ctx.U32[1], value, min, max);
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}
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
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Id result{};
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if (ctx.profile.has_broken_spirv_clamp) {
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result = ctx.OpUMax(ctx.U32[1], ctx.OpUMin(ctx.U32[1], value, max), min);
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} else {
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result = ctx.OpUClamp(ctx.U32[1], value, min, max);
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}
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitSLessThan32(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitSLessThan64(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitULessThan32(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpULessThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitULessThan64(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpULessThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpIEqual(ctx.U1[1], lhs, rhs);
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}
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Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThanEqual(ctx.U1[1], lhs, rhs);
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}
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Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpULessThanEqual(ctx.U1[1], lhs, rhs);
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}
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Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpUGreaterThan(ctx.U1[1], lhs, rhs);
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}
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Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpINotEqual(ctx.U1[1], lhs, rhs);
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}
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Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThanEqual(ctx.U1[1], lhs, rhs);
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}
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Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpUGreaterThanEqual(ctx.U1[1], lhs, rhs);
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}
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} // namespace Shader::Backend::SPIRV
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