mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-12-12 14:48:52 +00:00
shader_recompiler: Implement fallback path for missing shaderFloat16 support. (#3604)
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@@ -708,14 +708,10 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2) {
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return Inst(Opcode::CompositeConstructU32x2, e1, e2);
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case Type::U32x2:
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return Inst(Opcode::CompositeConstructU32x2x2, e1, e2);
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case Type::F16:
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return Inst(Opcode::CompositeConstructF16x2, e1, e2);
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case Type::F32:
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return Inst(Opcode::CompositeConstructF32x2, e1, e2);
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case Type::F32x2:
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return Inst(Opcode::CompositeConstructF32x2x2, e1, e2);
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x2, e1, e2);
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default:
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ThrowInvalidType(e1.Type());
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}
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@@ -728,12 +724,8 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu
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switch (e1.Type()) {
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case Type::U32:
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return Inst(Opcode::CompositeConstructU32x3, e1, e2, e3);
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case Type::F16:
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return Inst(Opcode::CompositeConstructF16x3, e1, e2, e3);
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case Type::F32:
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return Inst(Opcode::CompositeConstructF32x3, e1, e2, e3);
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x3, e1, e2, e3);
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default:
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ThrowInvalidType(e1.Type());
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}
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@@ -748,12 +740,8 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu
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switch (e1.Type()) {
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case Type::U32:
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return Inst(Opcode::CompositeConstructU32x4, e1, e2, e3, e4);
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case Type::F16:
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return Inst(Opcode::CompositeConstructF16x4, e1, e2, e3, e4);
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case Type::F32:
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return Inst(Opcode::CompositeConstructF32x4, e1, e2, e3, e4);
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x4, e1, e2, e3, e4);
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default:
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ThrowInvalidType(e1.Type());
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}
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@@ -787,24 +775,12 @@ Value IREmitter::CompositeExtract(const Value& vector, size_t element) {
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return read(Opcode::CompositeExtractU32x3, 3);
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case Type::U32x4:
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return read(Opcode::CompositeExtractU32x4, 4);
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case Type::F16x2:
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return read(Opcode::CompositeExtractF16x2, 2);
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case Type::F16x3:
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return read(Opcode::CompositeExtractF16x3, 3);
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case Type::F16x4:
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return read(Opcode::CompositeExtractF16x4, 4);
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case Type::F32x2:
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return read(Opcode::CompositeExtractF32x2, 2);
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case Type::F32x3:
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return read(Opcode::CompositeExtractF32x3, 3);
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case Type::F32x4:
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return read(Opcode::CompositeExtractF32x4, 4);
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case Type::F64x2:
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return read(Opcode::CompositeExtractF64x2, 2);
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case Type::F64x3:
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return read(Opcode::CompositeExtractF64x3, 3);
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case Type::F64x4:
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return read(Opcode::CompositeExtractF64x4, 4);
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default:
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ThrowInvalidType(vector.Type());
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}
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@@ -824,24 +800,12 @@ Value IREmitter::CompositeInsert(const Value& vector, const Value& object, size_
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return insert(Opcode::CompositeInsertU32x3, 3);
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case Type::U32x4:
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return insert(Opcode::CompositeInsertU32x4, 4);
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case Type::F16x2:
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return insert(Opcode::CompositeInsertF16x2, 2);
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case Type::F16x3:
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return insert(Opcode::CompositeInsertF16x3, 3);
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case Type::F16x4:
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return insert(Opcode::CompositeInsertF16x4, 4);
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case Type::F32x2:
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return insert(Opcode::CompositeInsertF32x2, 2);
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case Type::F32x3:
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return insert(Opcode::CompositeInsertF32x3, 3);
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case Type::F32x4:
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return insert(Opcode::CompositeInsertF32x4, 4);
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case Type::F64x2:
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return insert(Opcode::CompositeInsertF64x2, 2);
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case Type::F64x3:
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return insert(Opcode::CompositeInsertF64x3, 3);
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case Type::F64x4:
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return insert(Opcode::CompositeInsertF64x4, 4);
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default:
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ThrowInvalidType(vector.Type());
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}
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@@ -862,12 +826,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x2);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x2);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x2);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x2);
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default:
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ThrowInvalidType(vector1.Type());
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}
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@@ -888,12 +848,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x3);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x3);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x3);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x3);
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default:
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ThrowInvalidType(vector1.Type());
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}
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@@ -916,12 +872,8 @@ Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, si
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x4);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x4);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x4);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x4);
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default:
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ThrowInvalidType(vector1.Type());
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}
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@@ -934,18 +886,10 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu
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switch (true_value.Type()) {
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case Type::U1:
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return Inst(Opcode::SelectU1, condition, true_value, false_value);
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case Type::U8:
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return Inst(Opcode::SelectU8, condition, true_value, false_value);
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case Type::U16:
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return Inst(Opcode::SelectU16, condition, true_value, false_value);
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case Type::U32:
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return Inst(Opcode::SelectU32, condition, true_value, false_value);
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case Type::U64:
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return Inst(Opcode::SelectU64, condition, true_value, false_value);
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case Type::F32:
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return Inst(Opcode::SelectF32, condition, true_value, false_value);
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case Type::F64:
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return Inst(Opcode::SelectF64, condition, true_value, false_value);
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default:
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UNREACHABLE_MSG("Invalid type {}", true_value.Type());
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}
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@@ -165,18 +165,6 @@ OPCODE(CompositeInsertU32x4, U32x4, U32x
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OPCODE(CompositeShuffleU32x2, U32x2, U32x2, U32x2, U32, U32, )
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OPCODE(CompositeShuffleU32x3, U32x3, U32x3, U32x3, U32, U32, U32, )
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OPCODE(CompositeShuffleU32x4, U32x4, U32x4, U32x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF16x2, F16x2, F16, F16, )
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OPCODE(CompositeConstructF16x3, F16x3, F16, F16, F16, )
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OPCODE(CompositeConstructF16x4, F16x4, F16, F16, F16, F16, )
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OPCODE(CompositeExtractF16x2, F16, F16x2, U32, )
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OPCODE(CompositeExtractF16x3, F16, F16x3, U32, )
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OPCODE(CompositeExtractF16x4, F16, F16x4, U32, )
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OPCODE(CompositeInsertF16x2, F16x2, F16x2, F16, U32, )
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OPCODE(CompositeInsertF16x3, F16x3, F16x3, F16, U32, )
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OPCODE(CompositeInsertF16x4, F16x4, F16x4, F16, U32, )
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OPCODE(CompositeShuffleF16x2, F16x2, F16x2, F16x2, U32, U32, )
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OPCODE(CompositeShuffleF16x3, F16x3, F16x3, F16x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF16x4, F16x4, F16x4, F16x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF32x2, F32x2, F32, F32, )
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OPCODE(CompositeConstructF32x3, F32x3, F32, F32, F32, )
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OPCODE(CompositeConstructF32x4, F32x4, F32, F32, F32, F32, )
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@@ -190,27 +178,11 @@ OPCODE(CompositeInsertF32x4, F32x4, F32x
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OPCODE(CompositeShuffleF32x2, F32x2, F32x2, F32x2, U32, U32, )
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OPCODE(CompositeShuffleF32x3, F32x3, F32x3, F32x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF32x4, F32x4, F32x4, F32x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF64x2, F64x2, F64, F64, )
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OPCODE(CompositeConstructF64x3, F64x3, F64, F64, F64, )
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OPCODE(CompositeConstructF64x4, F64x4, F64, F64, F64, F64, )
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OPCODE(CompositeExtractF64x2, F64, F64x2, U32, )
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OPCODE(CompositeExtractF64x3, F64, F64x3, U32, )
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OPCODE(CompositeExtractF64x4, F64, F64x4, U32, )
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OPCODE(CompositeInsertF64x2, F64x2, F64x2, F64, U32, )
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OPCODE(CompositeInsertF64x3, F64x3, F64x3, F64, U32, )
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OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, )
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OPCODE(CompositeShuffleF64x2, F64x2, F64x2, F64x2, U32, U32, )
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OPCODE(CompositeShuffleF64x3, F64x3, F64x3, F64x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF64x4, F64x4, F64x4, F64x4, U32, U32, U32, U32, )
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// Select operations
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OPCODE(SelectU1, U1, U1, U1, U1, )
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OPCODE(SelectU8, U8, U1, U8, U8, )
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OPCODE(SelectU16, U16, U1, U16, U16, )
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OPCODE(SelectU32, U32, U1, U32, U32, )
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OPCODE(SelectU64, U64, U1, U64, U64, )
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OPCODE(SelectF32, F32, U1, F32, F32, )
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OPCODE(SelectF64, F64, U1, F64, F64, )
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// Bitwise conversions
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OPCODE(BitCastU16F16, U16, F16, )
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@@ -403,12 +403,8 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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case IR::Opcode::UnpackSint2_10_10_10:
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return FoldInverseFunc(inst, IR::Opcode::PackSint2_10_10_10);
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case IR::Opcode::SelectU1:
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case IR::Opcode::SelectU8:
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case IR::Opcode::SelectU16:
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case IR::Opcode::SelectU32:
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case IR::Opcode::SelectU64:
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case IR::Opcode::SelectF32:
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case IR::Opcode::SelectF64:
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return FoldSelect(inst);
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case IR::Opcode::FPNeg32:
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FoldWhenAllImmediates(inst, [](f32 a) { return -a; });
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@@ -563,15 +559,6 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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case IR::Opcode::CompositeExtractF32x4:
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return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF32x4,
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IR::Opcode::CompositeInsertF32x4);
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case IR::Opcode::CompositeExtractF16x2:
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return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x2,
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IR::Opcode::CompositeInsertF16x2);
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case IR::Opcode::CompositeExtractF16x3:
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return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x3,
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IR::Opcode::CompositeInsertF16x3);
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case IR::Opcode::CompositeExtractF16x4:
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return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x4,
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IR::Opcode::CompositeInsertF16x4);
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case IR::Opcode::ConvertF32F16:
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return FoldConvert(inst, IR::Opcode::ConvertF16F32);
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case IR::Opcode::ConvertF16F32:
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@@ -50,32 +50,6 @@ IR::Value F32ToPackedF64(IR::IREmitter& ir, const IR::Value& raw) {
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static IR::Opcode Replace(IR::Opcode op) {
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switch (op) {
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case IR::Opcode::CompositeConstructF64x2:
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return IR::Opcode::CompositeConstructF32x2;
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case IR::Opcode::CompositeConstructF64x3:
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return IR::Opcode::CompositeConstructF32x3;
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case IR::Opcode::CompositeConstructF64x4:
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return IR::Opcode::CompositeConstructF32x4;
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case IR::Opcode::CompositeExtractF64x2:
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return IR::Opcode::CompositeExtractF32x2;
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case IR::Opcode::CompositeExtractF64x3:
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return IR::Opcode::CompositeExtractF32x3;
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case IR::Opcode::CompositeExtractF64x4:
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return IR::Opcode::CompositeExtractF32x4;
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case IR::Opcode::CompositeInsertF64x2:
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return IR::Opcode::CompositeInsertF32x2;
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case IR::Opcode::CompositeInsertF64x3:
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return IR::Opcode::CompositeInsertF32x3;
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case IR::Opcode::CompositeInsertF64x4:
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return IR::Opcode::CompositeInsertF32x4;
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case IR::Opcode::CompositeShuffleF64x2:
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return IR::Opcode::CompositeShuffleF32x2;
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case IR::Opcode::CompositeShuffleF64x3:
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return IR::Opcode::CompositeShuffleF32x3;
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case IR::Opcode::CompositeShuffleF64x4:
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return IR::Opcode::CompositeShuffleF32x4;
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case IR::Opcode::SelectF64:
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return IR::Opcode::SelectF64;
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case IR::Opcode::FPAbs64:
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return IR::Opcode::FPAbs32;
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case IR::Opcode::FPAdd64:
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@@ -73,6 +73,7 @@ void Visit(Info& info, const IR::Inst& inst) {
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break;
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case IR::Opcode::ConvertF16F32:
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case IR::Opcode::ConvertF32F16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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info.uses_fp16 = true;
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break;
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