mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-08-04 16:32:39 +00:00
Merge branch 'qt-style' of https://github.com/tomboylover93/shadPS4 into qt-style
This commit is contained in:
commit
29a363dd0d
@ -327,7 +327,7 @@ void PS4_SYSV_ABI sched_yield() {
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std::this_thread::yield();
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}
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int PS4_SYSV_ABI posix_pthread_once(PthreadOnce* once_control, void (*init_routine)()) {
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int PS4_SYSV_ABI posix_pthread_once(PthreadOnce* once_control, void PS4_SYSV_ABI (*init_routine)()) {
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for (;;) {
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auto state = once_control->state.load();
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if (state == PthreadOnceState::Done) {
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@ -696,6 +696,10 @@ spv::ImageFormat GetFormat(const AmdGpu::Image& image) {
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image.GetNumberFmt() == AmdGpu::NumberFormat::Uint) {
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return spv::ImageFormat::R32ui;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format32 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Sint) {
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return spv::ImageFormat::R32i;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format32 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
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return spv::ImageFormat::R32f;
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@ -98,8 +98,8 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
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break;
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case Opcode::S_BREV_B32:
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return S_BREV_B32(inst);
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case Opcode::S_BCNT1_I32_B64:
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return S_BCNT1_I32_B64(inst);
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case Opcode::S_BCNT1_I32_B32:
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return S_BCNT1_I32_B32(inst);
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case Opcode::S_FF1_I32_B32:
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return S_FF1_I32_B32(inst);
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case Opcode::S_AND_SAVEEXEC_B64:
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@ -579,7 +579,7 @@ void Translator::S_BREV_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.BitReverse(GetSrc(inst.src[0])));
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}
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void Translator::S_BCNT1_I32_B64(const GcnInst& inst) {
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void Translator::S_BCNT1_I32_B32(const GcnInst& inst) {
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const IR::U32 result = ir.BitCount(GetSrc(inst.src[0]));
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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@ -602,6 +602,8 @@ void Translator::S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& in
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return ir.GetVcc();
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case OperandField::ScalarGPR:
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return ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code));
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case OperandField::ExecLo:
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return ir.GetExec();
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default:
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UNREACHABLE();
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}
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@ -439,7 +439,8 @@ void Translator::SetDst64(const InstOperand& operand, const IR::U64F64& value_ra
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ir.SetVectorReg(IR::VectorReg(operand.code + 1), hi);
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return ir.SetVectorReg(IR::VectorReg(operand.code), lo);
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case OperandField::VccLo:
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UNREACHABLE();
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ir.SetVccLo(lo);
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return ir.SetVccHi(hi);
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case OperandField::VccHi:
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UNREACHABLE();
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case OperandField::M0:
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@ -110,7 +110,7 @@ public:
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void S_MOV_B64(const GcnInst& inst);
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void S_NOT_B64(const GcnInst& inst);
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void S_BREV_B32(const GcnInst& inst);
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void S_BCNT1_I32_B64(const GcnInst& inst);
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void S_BCNT1_I32_B32(const GcnInst& inst);
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void S_FF1_I32_B32(const GcnInst& inst);
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void S_GETPC_B64(u32 pc, const GcnInst& inst);
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void S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst);
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@ -172,6 +172,7 @@ void ConvertTileToLinear(u8* dst, const u8* src, u32 width, u32 height, bool is_
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vk::Format DemoteImageFormatForDetiling(vk::Format format) {
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switch (format) {
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case vk::Format::eR8Uint:
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case vk::Format::eR8Unorm:
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return vk::Format::eR8Uint;
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case vk::Format::eR4G4B4A4UnormPack16:
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